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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

I2C AC Electrical Specifications

Notes:

1. For more information, see the I 2C-Bus specification by Philips Semiconductor [1].

2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling

edge of SCL.

3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT > 250 ns must then be met. This will automatically be the

case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line tRMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.

I2C Timing Waveforms

Figure 12 I2C Timing Waveforms

Signal

Symbol Reference

Edge

Standard

Mode

Fast

Mode

Unit

Min Max Min Max

I2C(1,4)

SCL

fSCL

none

0

100

0

400

kHz

tHD;STA

4.0

—

0.6

—

us

tR

—

1000

—

300

us

tF

—

300

—

300

us

SDA(2,3)

tSV;DAT

SCL rising

250

—

100

—

us

tHD;DAT

03.45

0

0.9

us

tR

—

1000

10

300

us

tF

—

300

10

300

us

Start or repeated start

condition

tSU;STA

SDA falling

4.7

—

0.6

—

us

tSU;STO

4.0

—

0.6

—

us

Stop condition

tSU;STO

SDA rising

4.0

—

0.6

—

us

Bus free time between a

stop and start condition

tBUF

4.7

—

1.3

—

us

Capacitive load for each

bus line

CB

—

400

—

400

pF

Table 14 Specifications of the SDA and SCL Bus Lines for F/S-mode I2C -bus Devices

tSU;STO

tHD;STA

tSU;STA

tSU;DAT

tHD;DAT

tHIGH

tHD;STA

tLOW

SDA

SCL

tBUF