P25Q64LE datasheet(12/96 Pages) PUYA

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P25Q64LE Datasheet

Puya Semiconductor

Page 12 of 96

5.4

AC Characteristics for Program and Erase

Table 5-4 AC parameters for program and erase(Ta=-40°C to +85°C)

Sym.

Parameter

1.65V to 2.0V

Units

Min.

Typ.

Max.

TESL(6)

Erase Suspend Latency

TPSL(6)

Program Suspend Latency

TPRS(4)

Latency between Program Resume and next Suspend

TERS(5)

Latency between Erase Resume and next Suspend

tPP

Page program time (up to 256 bytes)

tPE

Page erase time

tSE

Sector erase time

tBE1

Block erase time for 32K bytes

tBE2

Block erase time for 64K bytes

tCE

Chip erase time

Note

1. tCH + tCL must be greater than or equal to 1/ Frequency.

2. Typical values given for TA=25°C.

Not 100% tested.

3. Only applicable as a constraint for a WRSR instruction.

4. Program operation may be interrupted as often as system request. The minimum timing of tPRS must be

observed before issuing the next program suspend command. However, in order for an Program operation to

make progress, tPRS ≥ 350us must be included in resume-to-suspend loop(s). Not 100% tested.

5. Erase operation may be interrupted as often as system request. The minimum timing of tERS must be

observed before issuing the next erase suspend command. However, in order for an Erase operation to make

progress, tERS ≥ 350us must be included in resume-to-suspend loop(s). Notes. Not 100% tested.

6. Latency time is required to complete Erase/Program Suspend operation.

7. The value guaranteed by characterization, not 100% tested in production.

Figure 5-4 Serial Input Timing

SCLK

CS#

MSB

High-Z

LSB

tCHSL

tSLCH

tDVCH

tCHDX

tSHCH

tCHSH

tCHCL

tCLCH

tSHSL

tCLH tCLL

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