P25Q64LE datasheet(21/96 Pages) PUYA

21 / 96 page

P25Q64LE Datasheet

Puya Semiconductor

Page 21 of 96

Quad SPI

The P25Q64LE supports Quad SPI operation when using

the “Quad Output Fast Read”,” Quad I/O Fast

Read”(6BH,EBH) commands. These commands allow data to be transferred to or from the device at four

times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become

bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 andIO3. Quad SPI commands

require the non-volatile Quad Enable bit(QE) in Status Register to be set.

QPI

The P25Q64LE supports Quad Peripheral Interface (QPI) operations only when the device is switched from

Standard/Dual/Quad SPI mode to QPI mode using

the “Enable the QPI (38H)”command. The QPI mode

utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are

exclusive. Only one mode can be active at any given times. “Enable the QPI(38H)”and “Disable the

QPI(FFH)”commands are used to switch between these two modes. Upon power-up and after software reset

using “”Reset (99H)”command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI

mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set.

Software Reset & Hardware RESET# pin

The P25Q64LE can be reset to the initial power-on state by a software Reset sequence, either in SPI mode

or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h). If

the command sequence is successfully accepted, the device will take approximately 30uS (tReady) to reset.

No command will be accepted during the reset period.

The P25Q64LE can also be configured to utilize a hardware RESET# pin. The HOLD/RST bit in the

Configure Register is the configuration bit for HOLD# pin function or RESET# pin function. When

HOLD/RST=0 (factory default), the pin acts as a HOLD# pin as described above; when HOLD/RST=1, the pin

acts as a RESET# pin. Drive the RESET# pin low for a minimum period of ~1us (tRESET*) will reset the

device to its initial power-on state. Any on-going Program/Erase operation will be interrupted and data

corruption may happen. While RESET# is low, the device will not accept any command input.

If QE bit is set to 1, the HOLD or RESET function will be disabled, the pin will become one of the four data

I/O pins.

Hardware RESET# pin has the highest priority among all the input signals. Drive RESET# low for a minimum

period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status of

other SPI signals (/CS, CLK, IOs, WP# and/or HOLD#).

Note:

1. While a faster RESET# pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us

minimum is recommended to ensure reliable operation.

2. There is an internal pull-up resistor for the dedicated RESET# pin. If the reset function is not needed, this

pin can be left floating in the system.

P25Q64LE Datasheet(PDF) 21 Page - Puya Semiconductor Co., Ltd.