87421 Data Sheet

©2016 Integrated Device Technology, Inc

June 24, 2016

4

TABLE 5. AC CHARACTERISTICS, V

DD

= 3.3V±5%, TA = -40°C TO 85°C

TABLE 4D. LVDS DC CHARACTERISTICS, V

DD

= 3.3V±5%, TA = -40°C TO 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

CLK

Clock Input Frequency

1

GHz

t

PD

Propagation Delay;

NOTE 1

CLK to Q (Dif)

1.0

1.7

ns

tsk(pp)

Part-to-Part Skew; NOTE 2, 3

500

ps

t

JIT

Additive Phase Noise, RMS;

refer to Additive Phase Jitter Section

155.52MHz, Integration Range:

12kHz – 20MHz

0.17

ps

t

R

/ t

F

Output Rise/Fall Time

20% to 80%

150

500

ps

odc

Output Duty Cycle

f

IN

< 500MHz

43

57

%

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

OD

Differential Output Voltage

350

470

540

mV

Δ V

OD

V

OD

Magnitude Change

50

mV

V

OS

Offset Voltage

1.1

1.25

1.4

V

Δ V

OS

V

OS

Magnitude Change

50

mV