SC18IS600_601_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 13 December 2006

18 of 28

NXP Semiconductors

SC18IS600/601

9.

Dynamic characteristics

[1]

Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

[2]

SCL and SDA do not have glitch suppression circuits.

Table 12.

Dynamic characteristics

Symbol

Parameter

Conditions

Variable clock

Min

Max

Min

Max

internal RC oscillator

frequency (SC18IS600)

nominal f = 7.3728 MHz; trimmed to

±1 % at T

7.189

7.557

7.189

7.557

MHz

External clock input (SC18IS601); see Figure 22

oscillator frequency

0

12

-

-

MHz

clock cycle time

83

-

-

-

ns

clock HIGH time

22

22

-

ns

clock LOW time

22

22

-

ns

clock rise time

-

8

-

8

ns

clock fall time

-

8

-

8

ns

Glitch filter

glitch rejection time

RESET pin

-

50

-

50

ns

any pin except RESET

-

15

-

15

ns

signal acceptance time

RESET pin

125

-

125

-

ns

any pin except RESET

50

-

50

-

ns

SPI slave interface

SPI operating frequency 2.0 MHz

0

fosc

0

2.0

MHz

SPI cycle time

2.0 MHz

6

-

500

-

ns

SPI enable lead time

2.0 MHz

4

-

4

-

µs

SPI enable lag time

4

-

4

-

µs

SPICLK HIGH time

3

-

190

-

ns

SPICLK LOW time

3

-

190

-

ns

SPI data setup time

100

-

100

-

ns

SPI data hold time

100

-

100

-

ns

SPI access time

0

120

0

120

ns

SPI disable time

2.0 MHz

0

240

-

240

ns

SPI enable to output

data valid time

2.0 MHz

0

240

-

240

ns

3.0 MHz

0

167

-

167

ns

SPI output data hold

time

0-

0

-

ns

SPI rise time

SPI outputs (SPICLK, MOSI, MISO)

-

100

-

100

ns

SPI inputs (SPICLK, MOSI, MISO,

SS)

-

2000

-

2000

ns

SPI fall time

SPI outputs (SPICLK, MOSI, MISO)

-

100

-

100

ns

SPI inputs (SPICLK, MOSI, MISO,

SS)

-

2000

-

2000

ns