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AD9640/PCB Datasheet(PDF) 37 Page - Analog Devices

Part # AD9640/PCB
Description  14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
PDF  41 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9640/PCB Datasheet(HTML) 37 Page - Analog Devices

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Preliminary Technical Data
AD9640
Rev. PrD | Page 37 of 41
Addr.
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
106
Fine Upper
Threshold
Register 0 (local)
Fine Upper Threshold [7:0]
0x00
107
Fine Upper
Threshold
Register 1 (local)
X
X
X
Fine Upper Threshold [12:8]
0x00
108
Fine Lower
Threshold
Register 0 (local)
Fine Lower Threshold [7:0]
0x00
109
Fine Lower
Threshold
Register 1 (local)
X
X
X
Fine Lower Threshold [12:8]
0x00
10A
Increase Gain
Dwell Time
Register 0 (local)
IncreaseGain Dwell Time [7:0]
0x00
In ADC Clock
Cycles
10B
Increase Gain
Dwell Time
Register 1 (local)
IncreaseGain Dwell Time [15:8]
0x00
In ADC Clock
Cycles
10C
Signal monitor
DC Correction
Control (global)
X
DC
Correction
Freeze
DC Correction Bandwidth [3:0]
DC
Correction
for Signal
Path
Enable
DC
Correction
for PM
Enable
0x00
10D
Signal monitor
DC Value
Channel A
Register 0
(global)
DC Value Channel A [7:0]
Read only
10E
Signal monitor
DC Value
Channel A
Register 1
(global)
X
X
DC Value Channel A [13:8]
Read only
10F
Signal monitor
DC Value
Channel B
Register 0
(global)
DC Value Channel B [7:0]
Read only
110
Signal monitor
DC Value
Channel B
Register 1
(global)
DC Value Channel A [13:8]
Read only
111
Signal monitor
SPORT Control
(global)
X
RMS
Magnitude
Output
Enable
Peak
Power
Output
Enable
Threshold
Crossing
Output
Enble
SPORT Clock Divide
00 = Undefined
01 = divide by 2
10 = divide by 4
11 = divide by 8
SPORT
SCLK
Sleep
SPORT
Enable
0x04
112
Signal monitor
Control (global)
Enable
Complex
Power
Calculation
Mode
X
X
X
MS Mode
0 = RMS
1 = MS
Signal monitor Mode
00 = RMS/MS
Magnitude
01 = Peak Power
1x = Threshold Count
Signal
monitor
Enable
0x00
113
Signal monitor
Period Register 0
(global)
Signal monitor Period [7:0]
0x80
In ADC Clock
Cycles
114
Signal monitor
Period Register 1
(global)
Signal monitor Period [15:8]
0x00
In ADC Clock
Cycles
115
Signal monitor
Period Register 2
(global)
Signal monitor Period [23:16]
0x00
In ADC Clock
Cycles
116
Signal monitor
Signal monitor Value Channel A [7:0]
Read only



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