AD9640SLASHPCB datasheet(20/41 Pages) AD

20 / 41 page

AD9640

Preliminary Technical Data

Rev. PrD | Page 20 of 41

VREF

SENSE

0.5V

AD9640

VIN-A/VIN-B

VIN+A/VIN+B

SELECT

LOGI

ADC

CORE

Figure 10. Programmable Reference Configuration

If the internal reference of the AD9640 is used to drive multiple

converters to improve gain matching, the loading of the

reference by the other converters must be considered. Figure 11

depicts how the internal reference voltage is affected by loading.

Figure 11. VREF Accuracy vs. Load

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift

characteristics. Figure 12 shows the typical drift characteristics

of the internal reference in both 1 V and 0.5 V modes.

Figure 12. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

TBD kΩ load. The internal buffer generates the positive and

negative full-scale references for the ADC core. Therefore, the

external reference must be limited to a maximum of 1 V.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9640 sample clock inputs

(CLK+ and CLK-) should be clocked with a differential signal.

The signal is typically ac-coupled into the CLK+ and CLK- pins

via a transformer or capacitors. These pins are biased internally

(See Figure 13) and require no external bias.

1.2V

CLK+

CLK-

2pF

AVDD

Figure

Figure 13.Equivalent Clock Input Circuit

Clock Input Options

The AD9640 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, the jitter of the clock

source is of the most concern, as described in the Jitter

Considerations section.

Figure 14 shows one preferred method for clocking the AD9640

(at clock rates to 150MSPS). A low jitter clock source is

converted from single-ended to differential signal using an RF

transformer. The back-to-back Schottky diodes across the

transformer secondary limit clock excursions into the AD9640

to approximately 0.8 Vp-p differential. This helps prevent the

large voltage swings of the clock from feeding through to other

portions of the AD9640 while preserving the fast rise and fall

times of the signal, which are critical to a low jitter

performance.

0.1µF

SCHOTTKY

DIODES:

HMS2812

CLOCK

INPUT

50kΩ

100kΩ

~ CLK

CLK

ADC

AD9640

MIN-CIRCUITS

ADT1–1WT, 1:1Z

XFMR

AD9640/PCB Datasheet(PDF) 20 Page - Analog Devices

AD9640/PCB Datasheet(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Download

Link URL