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ADF4193

Rev. B | Page 15 of 28

FRAC/INT REGISTER (R0)

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

F12

DB13

F11

DB12

F10

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C3 (0)

DB1

C2 (0)

DB0

C1 (0)

8-BIT RF INT VALUE

12-BIT RF FRAC VALUE

CONTROL

BITS

F12

F11

F10

..........

FRACTIONAL VALUE (FRAC)

4092

4093

4094

4095

INTEGER VALUE (INT)

255

0 = < FRAC < MOD

Figure 29. FRAC/INT Register (R0)

R0, the FRAC/INT register, is used to program the synthesizer

output frequency. On the next PFD cycle following a write to

R0, the N divider section is updated with the new INT and

FRAC values. At the same time, the PLL automatically enters

fast lock mode and the charge pump current is increased to its

maximum value and stays at this value until the ICP timeout

counter times out, and switches SW1, SW2, and SW3 closed

and remains closed until the SW1, SW2, and SW3 timeout

counters time out.

Once all registers are programmed during the initialization

sequence (see Table 8), all that is required thereafter to program

a new channel is a write to R0. However, as described in the

Programming section, it can also be desirable to program R1

and R2 register settings on a channel-by-channel basis. These

settings are double buffered by the write to R0. This means that

while the data is loaded through the serial interface on the

respective R1 and R2 write cycles, the synthesizer is not updated

with their data until the next write to Register R0.

Control Bits

The three LSBs, Control Bit C3, Control Bit C2, and Control Bit C1,

should be set to 0, 0, 0, respectively, to select R0, the FRAC/INT

Reserved Bit

Bit DB23 is reserved and must be set to 0.

8-Bit INT Value

These eight bits set the INT value, which determines the integer

part of the feedback division factor. All integer values from 26

to 255 are allowed. See the Worked Example section.

12-Bit FRAC Value

The 12 FRAC bits set the numerator of the fraction that is input

to the Σ-Δ modulator. This, along with INT, specifies the new

frequency channel that the synthesizer locks to, as shown in the

Worked Example section. FRAC values from 0 to MOD − 1

cover channels over a frequency range equal to the PFD

reference frequency.

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