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ADF4193BCPZ Datasheet(PDF) 20 Page - Analog Devices |
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ADF4193BCPZ Datasheet(HTML) 20 Page - Analog Devices |
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20 / 28 page ![]() ADF4193 Rev. B | Page 20 of 28 POWER-DOWN REGISTER (R5) DB7 F5 DB6 F4 DB5 F3 DB4 F2 DB3 F1 DB2 C3 (1) DB1 C2 (0) DB0 C1 (1) CONTROL BITS PD DIFF AMP 0 1 F4 0 1 F5 DISABLED ENABLED DIFF AMP POWER-DOWN 0 1 F2 NORMAL OPERATION 3-STATE ENABLED CHARGE PUMP 3-STATE 0 1 F1 NORMAL OPERATION COUNTER RESET COUNTER RESET 0 1 F3 DISABLED ENABLED CHARGE PUMP POWER-DOWN Figure 34. Power-Down Register (R5) R5, the power-down register (C3, C2, C1 set to 1, 0, 1, respectively) can be used to software power down the PLL and differential amplifier sections. After power is initially applied, there must be writes to R5 to clear the power-down bits and to R2, R1, and R0 before the ADF4193 comes out of power-down. Power-Down Differential Amplifier When Bit DB6 and Bit DB7 are set high, the differential amplifier is put into power-down. When Bit DB6 and Bit DB7 are set low, normal operation is resumed. Power-Down Charge Pump Setting Bit DB5 high activates a charge pump power-down and the following events occur: • All active dc current paths are removed, except for the differential amplifier. • The R and N divider counters are forced to their load state conditions. • The charge pump is powered down with its outputs in three- state mode. • The digital lock detect circuitry is reset. • The RF IN input is debiased. • The reference input buffer circuitry is disabled. • The serial interface remains active and capable of loading and latching data. For normal operation, Bit DB5 should be set to 0, followed by a write to R0. CP Three-State When this bit is set high, the charge pump outputs are put into three-state. With the bit set low, the charge pump outputs are enabled. Counter Reset When this bit is set to 1, the counters are held in reset. For normal operation, this bit should be 0, followed by a write to R0. |
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