ADP3118

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THEORY OF OPERATION

The ADP3118 is a dual-MOSFET driver optimized for driving

two N-channel MOSFETs in a synchronous buck converter

topology. A single PWM input signal is all that is required to

properly drive the high-side and the low-side MOSFETs. Each

driver is capable of driving a 3 nF load at speeds up to 500 kHz.

A more detailed description of the ADP3118 and its features

follows. See Figure 1.

LOW-SIDE DRIVER

The low-side driver is designed to drive a ground-referenced

N-channel MOSFET. The bias to the low-side driver is

internally connected to the VCC supply and PGND.

When the driver is enabled, the driver’s output is 180° out of

phase with the PWM input. When the ADP3118 is disabled,

the low-side gate is held low.

HIGH-SIDE DRIVER

The high-side driver is designed to drive a floating N-channel

MOSFET. The bias voltage for the high-side driver is developed

by an external bootstrap supply circuit, which is connected

between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap

side gate drive voltage and to limit the switch node slew rate

(referred to as a Boot-Snap circuit, see the Application

Information section for more details). When the ADP3118 is

starting up, the SW pin is at ground, so the bootstrap capacitor

charges up to VCC through D1. When the PWM input goes

high, the high-side driver begins to turn on the high-side

To complete the cycle, Q1 is switched off by pulling the gate

down to the voltage at the SW pin. When the low-side

MOSFET, Q2, turns on, the SW pin is pulled to ground. This

allows the bootstrap capacitor to charge up to VCC again.

The high-side driver’s output is in phase with the PWM input.

When the driver is disabled, the high-side gate is held low.

OVERLAP PROTECTION CIRCUIT

The overlap protection circuit prevents both of the main power

switches, Q1 and Q2, from being on at the same time. This is

done to prevent shoot-through currents from flowing through

both power switches and the associated losses that can occur

during their on/off transitions. The overlap protection circuit

accomplishes this by adaptively controlling the delay from the

Q1 turn off to the Q2 turn on, and by internally setting the

delay from the Q2 turn off to the Q1 turn on.

To prevent the overlap of the gate drives during the Q1 turn off

and the Q2 turn on, the overlap circuit monitors the voltage at

the SW pin. When the PWM input signal goes low, Q1 begins

to turn off (after propagation delay). Before Q2 can turn on, the

overlap protection circuit makes sure that SW has first gone

high and then waits for the voltage at the SW pin to fall from

begins turn on. If the SW pin has not gone high first, the Q2

turn on is delayed by a fixed 150 ns. By waiting for the voltage

on the SW pin to reach 1 V or for the fixed delay time, the

overlap protection circuit ensures that Q1 is off before Q2 turns

on, regardless of variations in temperature, supply voltage, input

pulse width, gate charge, and drive current. If SW does not go

below 1 V after 190 ns, DRVL turns on. This can occur if the

current flowing in the output inductor is negative and is flowing

through the high-side MOSFET body diode.