MC68340 datasheet(226/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

5- 89

5.7 INSTRUCTION EXECUTION TIMING

This section describes the instruction execution timing of the CPU32. External clock

cycles are used to provide accurate execution and operation timing guidelines, but not

exact timing for every possible circumstance. This approach is used because exact

execution time for an instruction or operation depends on concurrence of independently

scheduled resources, on memory speeds, and on other variables.

An assembly language programmer or compiler writer can use the information in this

section to predict the performance of the CPU32. Additionally, timing for exception

processing is included so that designers of multitasking or real-time systems can predict

task-switch overhead, maximum interrupt latency, and similar timing parameters.

Instruction timing is given in clock cycles to eliminate clock frequency dependency.

5.7.1 Resource Scheduling

The CPU32 contains several independently scheduled resources. The organization of

these resources within the CPU32 is shown in Figure 5-30. Some variation in instruction

execution timing results from concurrent resource utilization. Because resource

scheduling is not directly related to instruction boundaries, it is impossible to make an

accurate prediction of the time required to complete an instruction without knowing the

entire context within which the instruction is executing.

5.7.1.1 MICROSEQUENCER. The microsequencer either executes microinstructions or

awaits completion of accesses necessary to continue microcode execution. The

microsequencer supervises the bus controller, instruction execution, and internal

processor operations such as calculation of EA and setting of condition codes. It also

initiates instruction word prefetches after a change of flow and controls validation of

instruction words in the instruction pipeline.

5.7.1.2 INSTRUCTION PIPELINE. The CPU32 contains a two-word instruction pipeline

where instruction opcodes are decoded. Each stage of the pipeline is initially filled under

microsequencer control and subsequently refilled by the prefetch controller as it empties.

Stage A of the instruction pipeline is a buffer. Prefetches completed on the bus before

stage B empties are temporarily stored in this buffer. Instruction words (instruction

operation words and all extension words) are decoded at stage B. Residual decoding and

execution occur in stage C.

Each pipeline stage has an associated status bit that shows whether the word in that

stage was loaded with data from a bus cycle that terminated abnormally.

5.7.1.3 BUS CONTROLLER RESOURCES. The bus controller consists of the instruction

prefetch controller, the write pending buffer, and the microbus controller. These three

resources transact all reads, writes, and instruction prefetches required for instruction

execution.

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