MC68340 datasheet(229/441 Pages) FREESCALE

229 / 441 page

5- 92

MC68340 USER’S MANUAL

MOTOROLA

The execution time attributed to instructions A, B, and C after considering the overlap is

illustrated in Figure 5-32. The overlap time is attributed to the execution time of the

completing instruction. The following equation shows the method for calculating the

overlap time:

Overlap = min (TailN, HeadN+1)

OVERLAP

PERIOD

(ABSORBED BY

INSTRUCTION A)

OVERLAP

PERIOD

(ABSORBED BY

INSTRUCTION B)

INSTRUCTION A

INSTRUCTION B

INSTRUCTION C

Figure 5-32. Attributed Instruction Times

5.7.1.5 EFFECTS OF WAIT STATES. The CPU32 access time for on-chip peripherals is

two clocks. While two-clock external accesses are possible when the bus is operated in a

synchronous mode, a typical external memory speed is three or more clocks.

All instruction times listed in this section are for word access only (unless an explicit

exception is given), and are based on the assumption that both instruction fetches and

operand cycles are to a two-clock memory. Any time a long access is made, time for the

additional bus cycle(s) must be added to the overall execution time. Wait states due to

slow external memory must be added to the access time for each bus cycle.

A typical application has a mixture of bus speeds—program execution from an off-chip

ROM, accesses to on-chip peripherals, storage of variables in slow off-chip RAM, and

accesses to external peripherals with speeds ranging from moderate to very slow. To

arrive at an accurate instruction time calculation, each bus access must be individually

considered. Many instructions have a head cycle count, which can overlap the cycles of

an operand fetch to slower memory started by a previous instruction. In these cases, an

increase in access time has no effect on the total execution time of the pair of instructions.

To trace instruction execution time by monitoring the external bus, note that the order of

operand accesses for a particular instruction sequence is always the same provided bus

speed is unchanged and the interleaving of instruction prefetches with operands within

each sequence is identical.

5.7.1.6 INSTRUCTION EXECUTION TIME CALCULATION. The overall execution time

for an instruction depends on the amount of overlap with previous and subsequent

instructions. To calculate an instruction time estimate, the entire code sequence must be

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68340 Datasheet(PDF) 229 Page - Freescale Semiconductor, Inc

MC68340 Datasheet(HTML) 229 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL