MC68340 datasheet(283/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

6- 33

6.7.6 Source Address Register (SAR)

The SAR is a 32-bit register that contains the address of the source operand used by the

DMA to access memory or peripheral registers. This register is accessible in either

supervisor or user space. The SAR can always be read or written to when the DMA

module is enabled (i.e., the STP bit in the MCR is cleared).

SAR1, SAR2

$78C, $7AC

A31

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

RESET:

UUUUUUUUUUUUUUUU

9876543210

A15

A14

A13

A12

A11

A10

RESET:

UUUUUUUUUUUUUUUU

U = Unaffected by reset

Supervisor/User

During the DMA read cycle, the SAR drives the address on the address bus. This register

can be programmed to increment (CCR SAPI bit set) or remain constant (CCR SAPI bit

cleared) after each operand transfer.

The register is incremented using unsigned arithmetic and will roll over if overflow occurs.

For example, if the register contains $FFFFFFFF and is incremented by 1, it will roll over

to $00000000. This register is incremented by 1, 2, or 4, depending on the size of the

operand and the memory starting address. If the operand size is byte, then the register is

always incremented by 1. If the operand size is word and the starting address is even-

word aligned, then the register is incremented by 2. If the operand size is long word and

the address is even-word aligned, then the register is incremented by 4. The SAR value

must be aligned to an even-word boundary if the transfer size is word or long word;

otherwise, the CSR CONF bit is set, and the transfer does not occur.

When read, this register always contains the next source address. If a bus error

terminates the transfer, this register contains the next source address that would have

been run had the error not occurred.

6.7.7 Destination Address Register (DAR)

The DAR is a 32-bit register that contains the address of the destination operand used by

the DMA to write to memory or peripheral registers. This register is accessible in either

supervisor or user space. The DAR can always be read or written to when the DMA

module is enabled (i.e., the STP bit in the MCR is cleared).

Freescale Semiconductor, Inc.

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