MC68340 datasheet(285/441 Pages) FREESCALE

285 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

6- 35

This register is decremented by 1, 2, or 4 for each successful operand transfer from

source to destination locations. When the BTC decrements to zero and no error has

occurred, the CSR DONE bit is set. In the external request mode, the

DONE

≈ handshake

line is also asserted when the BTC is decremented to zero.

If the operand size is byte, then the register is always decremented by 1. If the operand

size is word and the starting count is even word, the register is decremented by 2. If the

operand size is word and the byte count is not a multiple of 2, the CSR CONF bit is set,

and a transfer does not occur. If the operand size is long word and the count is even long

word, then the register is decremented by 4. If the operand size is long word and the byte

count is not a multiple of 4, the CSR CONF bit is set, and a transfer does not occur. If the

STR bit is set with a zero count in the BTC, the CONF bit is set, and the STR bit is

cleared.

When read, this register always contains the count for the next access. If a bus error

terminates the transfer, this register contains the count for the next access that would

have been run had the error not occurred.

6.8 DATA PACKING

The internal DHR is a 32-bit register that can serve as a buffer register for the data being

transferred during dual-address DMA cycles. No address is specified since this register

can not be addressed by the programmer. The DHR allows the data to be packed and

unpacked by the DMA during the dual-address transfer. For example, if the source

operand size is byte and the destination operand size is word, then two-byte read cycles

occur, followed by a one-word write cycle (see Figure 6-16). The two bytes of data are

buffered in the DHR until the destination (write) word cycle occurs. The DHR allows for

packing and unpacking of operands for the following sizes: bytes to words, bytes to long

words, words to long words, words to bytes, long words to bytes, and long words to words.

.. .

. .

BYTE0

BYTE1

BYTE0

BYTE1

BYTE2

BYTE3

BYTE0

BYTE2

BYTE1

BYTE3

BYTE0

BYTE1

BYTE2

BYTE3

BYTE0

BYTE1

BYTE2

BYTE3

BYTE0

BYTE1

SOURCE/DESTINATION

DESTINATION/SOURCE

Figure 6-16. Packing and Unpacking of Operands

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68340 Datasheet(PDF) 285 Page - Freescale Semiconductor, Inc

MC68340 Datasheet(HTML) 285 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL