MC68340 datasheet(312/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

7- 17

RxRDY bit and loads the character into the receiver holding register FIFO stack provided

the received A/D bit is a one (address tag). The character is discarded if the received A/D

bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to

the CPU32 via the receiver holding register stack during read operations.

In either case, the data bits are loaded into the data portion of the stack while the A/D bit

is loaded into the status portion of the stack normally used for a parity error (SR bit 5).

Framing error, overrun error, and break detection operate normally. The A/D bit takes the

place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this

mode may still contain error detection and correction information. One way to provide

error detection, if 8-bit characters are not required, is to use software to calculate parity

and append it to the 5-, 6-, or 7-bit character.

7.3.5 Bus Operation

This section describes the operation of the IMB during read, write, and interrupt

acknowledge cycles to the serial module. All serial module registers must be accessed as

bytes.

7.3.5.1 READ CYCLES. The serial module is accessed by the CPU32 with no wait states.

The serial module responds to byte reads. Reserved registers return logic zero during

reads.

7.3.5.2 WRITE CYCLES. The serial module is accessed by the CPU32 with no wait

states. The serial module responds to byte writes. Write cycles to read-only registers and

reserved registers complete in a normal manner without exception processing; however,

the data is ignored.

7.3.5.3 INTERRUPT ACKNOWLEDGE CYCLES. The serial module is capable of

arbitrating for interrupt servicing and supplying the interrupt vector when it has

successfully won arbitration. The vector number must be provided if interrupt servicing is

necessary; thus, the interrupt vector register (IVR) must be initialized. If the IVR is not

initialized, a spurious interrupt exception will be taken if interrupts are generated.

7.4 REGISTER DESCRIPTION AND PROGRAMMING

This section contains a detailed description of each register and its specific function as

well as flowcharts of basic serial module programming.

7.4.1 Register Description

The operation of the serial module is controlled by writing control bytes into the

appropriate registers. A list of serial module registers and their associated addresses are

shown in Figure 7-9. The mode, status, command, and clock-select registers are

duplicated for each channel to provide independent operation and control.

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MC68340 Datasheet(PDF) 312 Page - Freescale Semiconductor, Inc