MC68340 datasheet(433/441 Pages) FREESCALE

433 / 441 page

MOTOROLA

MC68330 USER’S MANUAL

Index-1

INDEX

— A —

A-Line Instructions, 5-47

A/D

Bit, 7-15–7-16, 7-23

Field, 5-73

A0 Signal, 3-6–3-13

Access Time Calculations, 10-6

Address

Access Time, 10-6

Bus Signals, 2-4, 3-4, 3-16

Error Exception, 3-7, 3-39, 5-42–5-43, 5-45–5-46

Mask Register Example, 4-33

Mask Registers, 4-31, 4-37

Registers, 5-10, 5-13

Space Bits, 4-20

Space Block Size, 4-2, 4-3, 4-14

Spaces, 2-5, 3-3–3-4, 4-2, 4-20, 4-30–4-31, 6-32

Strobe Signal, 2-6, 3-2, 3-4, 3-14–3-21, 3-44, 3-46,

4-22

with Postincrement, 5-14

with Predecrement, 5-14

Advantages, 10-13

Alternate Function Code Registers, 5-10

Applications Profile, 10-10

Arithmetic/Logical Instruction Timing Table, 5-102–

5-104

Assert RTS Command, 7-28–7-29

Asynchronous

Inputs, 3-1–3-2, 3-14–3-15, 3-44

Operation, 3-14

Setup and Hold Times, 3-2, 3-15, 3-18–3-21,10-7

ATEMP Register, 5-67

Automatic Echo Modes, 7-14, 7-38

Autovector

Operation Timing, 3-31

Signal, 2-6, 3-5, 3-29, 3-32, 4-6

Auxiliary Control Register, 7-18, 7-26–7-27, 7-32, 7-46

— B —

B Bits, 5-56, 5-57–5-58

B/C Bits, 7-23–7-24, 7-47

Background Debug Mode, 5-64–5-65, 5-94

Command Execution, 5-67

Command Summary, 5-75–5-76

Serial Interface, 5-68–5-69

Background Processing State, 5-7, 5-37, 5-64–5-73,

5-95–5-101

Base Address Bits, 4-20

Base Address Registers, 4-14, 4-30, 4-33, 4-37

Battery Operation, 10-10

Baud Rate

Clock, 7-2, 7-26–7-27

Generator, 7-3, 7-8

BB Bits, 6-4, 6-29, 6-38

BDM Sources, 5-66

BED Bit, 6-27, 6-27, 6-30–6-31, 6-37

BERR Signal, 5-45–5-47

BES Bit, 6-20, 6-31, 6-37

BFC Bits, 4-30

BGND Instruction, 5-66

Binary-Coded Decimal

Extended Instructions Timing Table, 5-106

Instructions, 5-26

Bit Manipulation Instructions, 5-25

Timing Table, 5-109

Bit Set/Reset Command, 7-37

Bits per Character, 7-23

BKPT Signal, 5-65–5-66, 5-68, 5-71–5-72

BKPT_TAG, 5-72

Block Mode, 7-13, 7-23

BME Bit, 4-6, 4-25, 4-37

BMT Bits, 4-25–4-26, 4-37

Boot ROM, 4-14–4-15, 4-36

Boundary Scan

Bit Definitions, 9-4

Break Condition, 7-11

Breakpoint Acknowledge Cycle

Operation, 3-22

Flowchart, 3-24

Timing, Opcode Returned, 3-25

Timing, Exception Signaled, 3-26

Breakpoint Exception, 5-42, 5-46–5-47, 5-53

Breakpoint Instruction, 3-22, 5-28, 5-40, 5-42,

5-46, 5-63, 5-94, 5-97

Breakpoint Signal, 2-10, 3-22, 3-24, 6-31

BRG Bit, 7-32, 7-46

BRKP Bit, 6-20, 6-27, 6-31, 6-37–6-38

Burst Mode Transfers, 6-5

Bus

Arbitration

Operation, 3-40, 3-41–3-45

Flowchart, 3-41

Interaction with Show Cycles, 3-44

Control, 3-44

State Diagram 3-45

Bandwidth, 6-4–6-5, 6-29

Controller Operation, 5-89–5-90

Cycle Termination Response Time, 4-6, 4-30, 4-32

Cycle Termination, 3-34–3-36, 3-47

Cycle, 3-2

Error Exception, 5-45

Error Signal, 2-8, 3-5, 3-14–3-15, 3-22, 3-24, 3-30,

3-32–3-37, 3-44, 4-4, 4-6, 4-22, 4-30

Error Stack Frame, 5-60–5-63

Errors

Types, 3-34

Timing, without

DSACK

≈, 3-35

Timing, Late Bus Error, 3-36

Resulting in Double Bus Faults, 3-39

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