AD5362BSTZ datasheet(18/25 Pages) AD

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AD5362/AD5363

Preliminary Technical Data

Rev. P

rF | Page 18 of 25

SERIAL INTERFACE

The AD5362/AD5363 contains an SPI-compatible interface

operating at clock frequencies up to 50MHz (20MHz for read

operations). To minimize both the power consumption of the

device and on-chip digital noise, the interface powers up fully

only when the device is being written to, that is, on the falling

edge of SYNC. The serial interface is 2.5 V LVTTL compatible

when operating from a 2.3 V to 3.6 V DVCC supply. It is

controlled by four pins, as follows.

SYNC

Frame synchronization input.

SDI

Serial data input pin.

SCLK

Clocks data in and out of the device.

SPI WRITE MODE

The AD5362/AD5363 allows writing of data via the serial

interface to every register directly accessible to the serial

interface, which is all registers except the X2A and X2B

registers and the DAC registers. The X2A and X2B registers are

updated when writing to the X1A, X1B, M and C registers, and

the DAC registers are updated by LDAC.

The serial word (see Tables 7 and 8) is 24 bits long. 16(14) of

these bits are data bits, five bits are address bits, and two bits are

mode bits that determine what is done with the data.

The serial interface works with both a continuous and a burst

(gated) serial clock. Serial data applied to SDI is clocked into

the AD5362/AD5363 by clock pulses applied to SCLK. The first

falling edge of SYNC starts the write cycle. At least 24 falling

clock edges must be applied to SCLK to clock in 24 bits of data,

before SYNC is taken high again. If SYNC is taken high before

the 24th falling clock edge, the write operation will be aborted.

If a continuous clock is used, and PEC mode isn’t used, SYNC

must be taken high before the 25th falling clock edge. This

inhibits the clock within the AD5362/AD5363. If more than 24

falling clock edges are applied before SYNC is taken high again,

the input data will be corrupted. If an externally gated clock of

exactly 24 pulses is used, SYNC may be taken high any time

after the 24th falling clock edge.

The input register addressed is updated on the rising edge of

SYNC. In order for another serial transfer to take place, SYNC

must be taken low again.

As mentioned previously the value of the X2 (A or B) register is

calculated each time the user writes new data to the

corresponding X1, C or M registers. The calculation is

performed by a three stage process. The first two stages take

500ns each and the third stage takes 250ns. When the write to

one of the X1, C or M registers is complete the calculation

process begins. If the write operation involves the update of a

single DAC channel the user is free to write to another register

provided that the write operation doesn’t finish until the first

stage calculation is complete, i.e. 500ns after the completion of

the first write operation. If a group of channels is being updated

by a single write operation the first stage calculation will be

repeated for each channel, taking 500ns per channel. In this

case the user should not complete the next write operation until

this time has elapsed.

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy

environments, the AD5362/AD5363 offers the option of error

checking based on an 8-bit (CRC-8) cyclic redundancy check.

The device controlling the AD5362/AD5363 should generate an

8-bit frame check sequence using the polynomial C(x) = x8 + x2

+ x1 +1. This is added to the end of the data word, and 32 data

bits are sent to the AD5362/AD5363 before taking SYNC high.

If the AD5362/AD5363 sees a 32-bit data frame, it will perform

the error check when SYNC goes high. If the check is valid,

then the data will be written to the selected register. If the error

check fails, the Packet Error Check output (PEC) will go low

and bit 3 of the Control Register is set. After reading this

high again.

SYNC

SCLK

DIN

24-BIT DATA TRANSFER - NO ERROR CHECKING

SYNC

SCLK

DIN

MSB

D23

LSB

MSB

D31

LSB

UPDATE ON SYNC HIGH

UPDATE AFTER SYNC HIGH

ONLY IF ERROR CHECK PASSED

24-BIT DATA

24 BIT DATA

24-BIT DATA TRANSFER WITH ERROR CHECKING

8-BIT FCS

PEC

PEC GOES LOW IF

ERROR CHECK FAILS

5360-0010

Figure 10. SPI Write With and Without Error Checking

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