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AD5371BBCZ Datasheet(PDF) 6 Page - Analog Devices |
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AD5371BBCZ Datasheet(HTML) 6 Page - Analog Devices |
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6 / 25 page  Preliminary Technical Data AD5371 Rev. P rF | Page 6 of 25 TIMING CHARACTERISTICS DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; RL = Open Circuit; Gain (m), Offset (c) and DAC Offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. SPI INTERFACE ( Figure 4 and Figure 5) Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description t1 20 ns min SCLK Cycle Time. t2 8 ns min SCLK High Time. t3 8 ns min SCLK Low Time. t4 11 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time. t5 20 ns min Minimum SYNC High Time. t6 10 ns min 24th SCLK Falling Edge to SYNC Rising Edge. t7 5 ns min Data Setup Time. t8 5 ns min Data Hold Time. t93 42 ns max SYNC Rising Edge to BUSY Falling Edge. t10 1.25 µs max BUSY Pulse Width Low (Single-Channel Update.) See Table 7 t11 500 ns max Single-Channel Update Cycle Time t12 20 ns min 24th SCLK Falling Edge to LDAC Falling Edge. t13 10 ns min LDAC Pulse Width Low. t14 3 µs max BUSY Rising Edge to DAC Output Response Time. t15 0 ns min BUSY Rising Edge to LDAC Falling Edge. t16 3 µs max LDAC Falling Edge to DAC Output Response Time. t17 20/30 µs typ/max DAC Output Settling Time. t18 125 ns max CLR/RESET Pulse Activation Time. t19 30 ns min RESET Pulse Width Low. t20 400 µs max RESET Time Indicated by BUSY Low. t21 270 ns min Minimum SYNC High Time in Readback Mode. t225 25 ns max SCLK Rising Edge to SDO Valid. LVDS INTERFACE ( Figure 6) Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description t1 10 ns min SCLK Cycle Time. t2 4 ns min SCLK Pulse Width High and Low Time. t3 2 ns min SYNC to SCLK Setup Time. t4 2 ns min Data Setup Time. t5 2 ns min Data Hold Time. t6 2 ns min SCLK to SYNC Hold Time. 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. 3 See Figure 4 and Figure 5. 4 This is measured with the load circuit of Figure 2. 5 This is measured with the load circuit of Figure 3. TO OUTPUT PIN VCC RL 2.2k Ω CL 50pF VOL 200µA 200µA 50pF CL IOL IOL VOH(min)-VOL (max) 2 TO OUTPUT PIN Figure 2. Load Circuit for BUSY Timing Diagram Figure 3. Load Circuit for SDO Timing Diagram |
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