Philips Semiconductors

Product specification

N-channel enhancement mode

BSP100

TrenchMOS

™ transistor

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

V

• Low on-state resistance

• Fast switching

I

• High thermal cycling performance

• Low thermal resistance

R

R

GENERAL DESCRIPTION

PINNING

SOT223

N-channel

enhancement

mode

PIN

DESCRIPTION

field-effect transistor in a plastic

envelope

using

’trench’

1

gate

technology.

2

drain

Applications:-

• Motor and relay drivers

3

source

• d.c. to d.c. converters

• Logic level translator

4

drain (tab)

The BSP100 is supplied in the

SOT223

surface

mounting

package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DSS

Drain-source voltage

T

-

30

V

V

DGR

Drain-gate voltage

T

-30

V

V

GS

Gate-source voltage

-

± 20

V

I

D

Continuous drain current

T

25 ˚C

-

6

1

A

T

-

4.4

A

T

25 ˚C

-

3.2

A

I

DM

Pulsed drain current

T

-

24

A

P

D

Total power dissipation

T

-

8.3

W

T

Operating junction and

- 65

150

˚C

storage temperature

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R

th j-sp

Thermal resistance junction to

surface mounted, FR4

12

15

K/W

solder point

board

R

th j-amb

Thermal resistance junction to

surface mounted, FR4

70

-

K/W

ambient

board

d

g

s

4

1

23

1 Continuous current rating limited by package

February 1999

1

Rev 1.000