April 1995

8

Philips Semiconductors

Product specification

N-channel enhancement mode vertical

D-MOS transistor

BSP106

PACKAGE OUTLINES

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

SOT429

TO-247

98-03-24

0

10

20 mm

scale

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-247

SOT429

E

P

A

A1

β

b

12

3

e

e

b1

b2

c

Q

q

L

Y

R

D

S

L1

(1)

α

UNIT

A1

D

b

E

e

w

S

R

q

Q

P

LY

b2

b1

c

L1

(1)

DIMENSIONS (mm are the original dimensions)

A

β

α

mm

17

°

13

°

6

°

4

°

5.3

4.7

1.9

1.7

2.2

1.8

1.2

0.9

3.2

2.8

0.9

0.6

21

20

16

15

5.45

3.7

3.3

2.6

2.4

5.3

7.5

7.1

0.4

15.7

15.3

16

15

4.0

3.6

3.5

3.3

Note

1. Tinning of terminals are uncontrolled within zone L1.