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ISP1504CBS Datasheet(PDF) 21 Page - NXP Semiconductors |
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ISP1504CBS Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 84 page ![]() ISP1504A_ISP1504C_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 19 October 2006 21 of 84 NXP Semiconductors ISP1504A; ISP1504C ULPI HS USB OTG transceiver completed. After every reset, an RXCMD is sent to the link to update USB status information. After this sequence, the ULPI bus is ready for use and the link can start USB operations. If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1504 will drive a 60 MHz clock out from the CLOCK pin when DIR de-asserts. This is shown as CLOCK (output) in Figure 6. If no crystal is attached and a 60 MHz clock is driven into the CLOCK pin, DIR will de-assert when internal clocks have synchronized. This is shown as CLOCK (input) in Figure 6. The recommended power-up sequence for the link is as follows: • The link waits for 1 ms, ignoring all the ULPI pin status. • The link may start to detect DIR status level. If DIR is detected as LOW for three clock cycles, the link may send a RESET command. • The ULPI interface is ready for use. |
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