PCK940L datasheet(7/16 Pages) PHILIPS

7 / 16 page

PCK940L_1

Product data sheet

Rev. 01 — 4 April 2006

7 of 16

Philips Semiconductors

PCK940L

Low voltage 1 : 18 clock distribution chip

[1]

Tested using standard input levels, production tested at 150 MHz.

[2]

Across temperature and voltage ranges, includes output skew.

[3]

For a speciﬁc temperature and voltage, includes output skew.

Table 10.

Dynamic characteristics (3.3 V VCC, 2.5 V output)

Tamb =0 °Cto70 °C; VCC2 = 3.3 V ± 5 %; VCC1 = 2.5 V ± 5%

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

foper(max)

maximum operating frequency

250

MHz

tPLH

LOW-to-HIGH propagation

delay

PECL_CLK

≤ 150 MHz

[1] 2.0

2.8

4.0

LVCMOS_CLK

≤ 150 MHz

[1] 1.7

2.5

3.0

PECL_CLK > 150 MHz

2.0

2.9

4.0

LVCMOS_CLK > 150 MHz

1.8

2.5

3.3

tsk(o)

output skew time

output-to-output

PECL_CLK

[1] -

300

LVCMOS_CLK

[1] -

150

tsk(pr)

process skew time

part-to-part

PECL_CLK < 150 MHz

[1][2] -

1.5

LVCMOS_CLK < 150 MHz

[1][2] -

1.3

PECL_CLK > 150 MHz

[1][2] -

1.8

LVCMOS_CLK > 150 MHz

[1][2] -

1.5

PECL_CLK

[1][3] -

850

LVCMOS_CLK

[1][3] -

750

δo

output duty cycle

LCVMOS_CLK; input

δ =50%

fclk < 134 MHz

fclk ≤ 250 MHz

PECL_CLK; input

δ =50%

fclk < 134 MHz

fclk ≤ 250 MHz

rise time

output; from 0.5 V to 1.8 V

0.3

1.2

fall time

output; from 1.8 V to 0.5 V

0.3

1.2

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