LTM4643 datasheet(12/24 Pages) AD

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LTM4710-1

Rev. 0

For more information www.analog.com

The LTM4710-1 device is an inherently current mode-

controlled device, so that parallel modules will have very

good current sharing. This will balance the thermals on

all channels. Connect the RUN, COMP and PG pin of each

paralleling channel together and connect FB to VIN for

subordinary channels. Figure 17 shows an example of

parallel operation and pin connection.

Soft-Start/Output Voltage Tracking/

Temperature Monitoring

The SSTT pin function facilitates supply sequencing, lim-

its VIN inrush current and reduces start-up output over-

shoot. An internal 10µA charge up a capacitor on the SSTT

pin hence program the ramp rate of the output voltage.

SSTT pin can also be externally driven by another voltage

source. During the soft-start ramp, when the SSTT voltage

is below 0.5V, the output voltage will proportionally track

the SSTT pin voltage. When the SSTT voltage is above

0.5V, the SSTT pin will servo to a voltage proportional to

the LTM4710-1 die junction temperature (see Figure 2).

The SSTT capacitor is reset during shutdown, VIN UVLO

and over thermal shutdown.

DIE TEMP

(°C)

(V)

150

0.1

125

0.6

0.3

100

0.5

0.4

0.2

0.5

1.5

0.6

1.6

0.3

1.3

47101 F02

1.7

0.4

1.4

0.2

1.2

0.1

SSTT (V)

TEMP

MONITOR

~4mV/°C

SSTT PIN VOLTAGE

OPERATING RANGE

SOFT-START

AND TRACKING

Figure 2. Soft-Start and Temperature Monitor Operation

The total soft-start time can be calculated with Equation 5.

tSS = CSS •

500mV

10µA

(5)

where CSS is the capacitance on the SSTT pin. FCM is

disabled during the soft-start process to prevent the

current from reversing.

A default 10nF soft-start cap is connected to SSTT1

inside the module, resulting in a 0.5ms default start-up

time on channel 1. The presence of this cap is to simplify

customers’ design in most cases.

Output Power Good

When the LTM4710-1’s output voltage is within the –2%

and +10% window of the nominal regulation voltage, the

output is considered good, and the open-drain PG pin

goes high impedance and is typically pulled high with an

external resistor. Otherwise, the internal pull-down device

will pull the PG pin low. To prevent glitching both the

upper and lower thresholds, include 1% of hysteresis as

well as a built-in time delay, typically 100μs. The PG pin is

also actively pulled low during fault conditions: RUN pin

is low, VIN is too low or in thermal shutdown.

For multiphase applications, the PG pin is used for com-

munication between the main and sub-ordinary phases.

Connect the PG pins together and pull-up to VIN or VOUT

with an external resistor. PG pins MUST be pulled higher

than 490mV.

Stability Compensation

The LTM4710-1 has already been internally optimized and

compensated for all output voltages and capacitor combi-

nations including all ceramic capacitor applications when

COMPb is tied to COMPa.

Table 10 is provided for most application requirements

using the optimized internal compensation. For applica-

tions that need to achieve high bandwidth control loop

compensation with enough phase margin, a 68pF feed-for-

ward capacitor is recommended from VOUT to VFB pin. For

specific optimized requirement, disconnect COMPb from

COMPa and apply a Type II C-R-C compensation network

from COMPa to AGND to achieve external compensation.

The LTpowerCAD design tool can be downloaded online to

perform specific control loop optimization and analyze the

control stability and load transient performance.

RUN Enable

The LTM4710-1 has a precision threshold RUN pin to

enable or disable the switching. When forced low, the

RUN pin puts the LTM4710-1 into a low current shutdown

APPLICATIONS INFORMATION

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