EVAL-AD7797EB datasheet(17/24 Pages) AD

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AD7796/AD7797

Rev. A | Page 17 of 24

DIGITAL INTERFACE

As outlined in the On-Chip Registers section, the AD7796/

AD7797 programmable functions are controlled by a set of on-

chip registers. Data is written to these registers via the part’s

serial interface and read access to the on-chip registers is also

provided by this interface. All communication with the part

must start with a write to the communication register. After

power-on or reset, the device expects a write to its

communication register. The data written to this register

determines whether the next operation is a read or a write

operation, and determines the register where this operation

occurs. Therefore, write access to any of the other registers on

the part begins with a write operation to the communication

operation from any other register (except when continuous read

mode is selected) starts with a write to the communication

The serial interface of the AD7796/AD7797 consists of four

signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used

to transfer data into the on-chip registers, while DOUT/RDY is

used for accessing from the on-chip registers. SCLK is the serial

clock input for the device, and all data transfers (either on DIN

or DOUT/RDY) occur with respect to the SCLK signal. The

DOUT/RDY pin also operates as a data-ready signal, that is, the

line goes low when a new data-word is available in the output

data register update to indicate when not to read from the

device. This ensures that a data read is not attempted while the

used to decode the AD7796/AD7797 in systems where several

components are connected to the serial bus.

Figure 3 and Figure 4 show timing diagrams for interfacing to

the AD7796/AD7797 with CS being used to decode the part.

Figure 3 shows the timing for a read operation from the

AD7796/AD7797 output shift register, while Figure 4 shows the

timing for a write operation to the input shift register. It is

possible to read the same word from the data register several

times, even though the DOUT/RDY line returns high after the

first read operation. However, care must be taken to ensure that

the read operations have been completed before the next output

update occurs. In continuous read mode, the data register can

be read only once.

The serial interface can operate in 3-wire mode by tying CS low.

In this case, the SCLK, DIN, and DOUT/RDY lines are used

to communicate with the AD7796/AD7797. The end of the

conversion can be monitored using the RDY bit in the status

controllers. If CS is required as a decoding signal, it can be

generated from a port pin. For microcontroller interfaces, it is

recommended that SCLK idle high between data transfers.

The AD7796/AD7797 can be operated with CS being used as a

frame synchronization signal. This scheme is useful for DSP

interfaces. In this case, the first bit (MSB) is effectively clocked

out by CS because CS normally occurs after the falling edge of

SCLK in DSPs. The SCLK can continue to run between data

transfers, provided the timing numbers are obeyed.

The serial interface can be reset by writing a series of 1s on the

DIN input. If a Logic 1 is written to the AD7796/AD7797 DIN

line for at least 32 serial clock cycles, the serial interface is reset.

This ensures that the interface can be reset to a known state if

the interface gets lost due to a software error or glitch in the

system. Reset returns the interface to the state where it is

expecting a write to the communication register. This operation

resets the contents of all registers to their power-on values.

Following a reset, the user should allow a period of 500 μs

before addressing the serial interface.

The AD7796/AD7797 can be configured to continuously

convert or to perform a single conversion. See Figure 14

through Figure 16.

EVAL-AD7797EB Datasheet(PDF) 17 Page - Analog Devices

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