AD8106ASTZ datasheet(21/28 Pages) AD

21 / 28 page

AD8106/AD8107

Rev. 0 | Page 21 of 28

EVALUATION BOARD

w = 0.008"

(0.2mm)

a = 0.008"

(0.2mm)

b = 0.024"

(0.6mm)

h = 0.011325"

(0.288mm)

t = 0.00135" (0.0343mm)

COMPONENT LAYER

SIGNAL ROUTING LAYER

POWER PLANE LAYER

BOTTOM LAYER

A 4-layer evaluation board is available for the AD8106/

AD8107. The same board and external components are used for

each device. The only difference is the device itself, which offers

a selection of a gain of unity or a gain of two through the analog

channels. This board has been carefully laid out and tested to

demonstrate the specified high speed performance of the

device. Figure 49 shows the schematic of the evaluation board.

Figure 50 shows the component side silkscreen. The layout of

the board’s four layers are given in:

Figure 48. Cross Section of Input and Output Traces

The board has 24 BNC-type connectors: 16 inputs and 8 outputs.

The connectors are arranged in a crescent around the device.

As shown in

•

Component Layer (see Figure 51)

Figure 53, this results in all 16 input signal traces

and all 8 signal output traces having the same length. This is

useful in tests such as all-hostile crosstalk where the phase

relationship and delay between signals needs to be maintained

from input to output.

•

Signal Routing Layer (see Figure 52)

•

Power Layer (see Figure 53)

•

Bottom Layer (see Figure 54)

The evaluation board package includes the following:

The three power supply pins, AVCC, DVCC, and AVEE, should

be connected to good quality, low noise, ±5 V supplies. While

the same ±5 V power supplies are used for analog and digital,

separate cables should be run for the power supply to the

evaluation board’s analog and digital power supply pins.

•

Fully populated board with BNC-type connectors.

•

Windows®-based software for controlling the board from a

PC via the printer port.

As a general rule, each power supply pin (or group of adjacent

power supply pins) should be locally decoupled with a 0.01 μF

capacitor. If there is a space constraint, decouple analog power

supply pins before digital power supply pins. A 0.1 μF capacitor

located reasonably close to the pins can be used to decouple a

number of power supply pins. Finally, a 10 μF capacitor should

be used to decouple power supplies as they come on to the board.

•

Custom cable to connect evaluation board to PC.

•

Disk containing Gerber files of board layout.

Optimized for video applications, all signal inputs and outputs

are terminated with 75 Ω resistors. Stripline techniques are used

to achieve a characteristic impedance on the signal input and

output lines, also of 75 Ω. Figure 48 shows a cross section of one

of the input or output tracks along with the arrangement of the

PCB layers. Note that unused regions of the four layers are filled

up with ground planes. As a result, the input and output traces,

in addition to having controlled impedances, are well shielded.

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