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3935 Datasheet(PDF) 5 Page - Allegro MicroSystems |
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3935 Datasheet(HTML) 5 Page - Allegro MicroSystems |
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5 / 16 page ![]() 3935 THREE-PHASE POWER MOSFET CONTROLLER www.allegromicro.com 5 ELECTRICAL CHARACTERISTICS: unless otherwise noted at T J = -40°C to +150°C, VBAT = 7 V to 16 V, V DD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active. Limits Characteristics Symbol Conditions Min Typ Max Units Control Logic Logic Input Voltages V I(1) Minimum high level input for logical “one” 2.0 – – V V I(0) Maximum low level input for logical “zero” – – 0.8 V Logic Input Currents I I(1) V I = VDD – – 500 µA I I(0) V I = 0.8 V 50 – – µA Input Hysteresis V hys 100 – 300 mV Logic Output High Voltage V O(H) I O(H) = -800 uA V DD-0.8 – – V Logic Output Low Voltage V I(L) I O(L) = 1.6 mA – – 0.4 V Gate Drives, GHx ( internal SOURCE or upper switch stages) Output High Voltage V DSL(H) GHx: I xU = -10 mA, Vsx = 0 V REG-2.26 – V REG V GLx: I xU = -10 mA, Vlss = 0 V REG-0.26 – V REG V Source Current (pulsed) I xU V SDU = 10 V, TJ = 25 °C – 800 – mA V SDU = 10 V, TJ = 135 °C 400 – – mA Source ON Resistance r SDU(on) I xU = -150 mA, Tj = 25 °C 4.0 – 10 Ω I xU = -150 mA, TJ = 135 °C 7.0 – 15 Ω Gate Drives, GLx ( internal SINK or lower switch stages) Sink Current (pulsed) I xL V DSL = 10 V, TJ = 25 °C – 850 – mA V DSL = 10 V, TJ = 135 °C 550 – – mA Sink ON Resistance r DSL(on) I xL = +150 mA, TJ = 25 °C 1.8 – 6.0 Ω I xL = +150 mA, TJ = 135 °C 3.0 – 7.5 Ω Gate Drives, GHx, GLx (General) Propagation Delay, Logic only t pd Logic input to unloaded GHx, GLx – – 150 ns Output Skew Time t sk(o) Grouped by edge, phase-to-phase – – 50 ns Dead Time t dead Between GHx, GLx transitions of same phase 75 – 180 ns (Shoot-Through Prevention) NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. For GH X: VSDU = VCX – VGHX, VDSL = VGHX – VSX, VDSL(H) = VCX – VSDU – VSX. For GL X: VSDU = VREG – VGLX, VDSL = VGLX – VLSS, VDSL(H) = VREG – VSDU – VLSS. |
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