7.6 Timing Requirements

At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) =

100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃,

unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tGI_VIT–

Glitch immunity VIT–

5% VIT– overdrive(1)

15

µs

tMR_PW

MR pin pulse duration to assert reset

100

ns

tP-WD

WDI pulse duration to start next frame (2)

VDD > VIT–

500

ns

tHD-WDEN

WD-EN hold time to enable or disable WD

operation (2)

VDD > VIT–

200

µs

tHD-SETx

SETx hold time to change WD timer setting

(2)

VDD > VIT–

150

µs

tWD

Watchdog timeout period

Orderable Option TPS35xxxxB

0.8

1

1.2

ms

Orderable Option TPS35xxxxC

4

5

6

Orderable Option TPS35xxxxD

9

10

11

Orderable Option TPS35xxxxE

18

20

22

Orderable Option TPS35xxxxF

45

50

55

Orderable Option TPS35xxxxG

90

100

110

Orderable Option TPS35xxxxH

180

200

220

Orderable Option TPS35xxxxI

0.9

1

1.1

s

Orderable Option TPS35xxxxJ

1.26

1.4

1.54

Orderable Option TPS35xxxxK

1.44

1.6

1.76

Orderable Option TPS35xxxxL

9

10

11

Orderable Option TPS35xxxxM

45

50

55

Orderable Option TPS35xxxxN

90

100

110

(1)

Overdrive % = [(VDD/ VIT–) – 1] × 100%

(2)

Not production tested

www.ti.com

TPS35-Q1

SLVSGE8A – NOVEMBER 2022 – REVISED JUNE 2023

Copyright © 2023 Texas Instruments Incorporated

Submit Document Feedback

9

Product Folder Links: TPS35-Q1