Nexperia

74HC02; 74HCT02

Quad 2-input NOR gate

4. Functional diagram

mna216

1A

1B

1Y

3

2

1

2A

2B

2Y

6

5

4

3A

3B

3Y

9

8

10

4A

4B

4Y

12

11

13

Fig. 1. Logic symbol

001aah084

2

1

3

5

4

≥1

6

≥1

8

10

≥1

9

11

13

≥1

12

Fig. 2. IEC logic symbol

mna215

A

B

Y

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

D package

SOT108-1 (SO14)

aaa-035251

1

2

3

4

5

6

7

8

10

9

12

11

14

13

VCC

4Y

4B

4A

3Y

3B

1Y

1A

1B

2Y

2A

2B

GND

3A

PW package

SOT402-1 (TSSOP14)

1Y

VCC

1A

4Y

1B

4B

2Y

4A

2A

3Y

2B

3B

GND

3A

aaa-035252

1

2

3

4

5

6

7

8

10

9

12

11

14

13

aaa-035253

Transparent top view

2B

3B

2A

3Y

2Y

4A

1B

4B

1A

4Y

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

BQ package

SOT762-1 (DHVQFN14)

GND(1)

aaa-035556

Transparent top view

1A 2

terminal 1

index area

1B

4B

3

12

2Y 4

2A 5

2B 6

4Y

13

4A

11

3Y

10

3B

9

BZ package

SOT8014-1 (DHXQFN14)

GND(1)

(1) This is not a ground pin. There is no electrical or mechanical requirement to solder

the pad. In case soldered, the solder land should remain floating or connected to GND.

74HC_HCT02

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2023. All rights reserved

Product data sheet

Rev. 8 — 9 February 2023

2 / 14