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FFT

-160

-140

-120

-100

-80

-60

-40

-20

0

20

0

100

200

300

400

500

f-Frequency-kHz

10kHzInput,

+VA =5V,

f =1MSPS,

V

=5V

s

ref

FFT

-160

-140

-120

-100

-80

-60

-40

-20

0

0

100

200

300

400

500

f-Frequency-kHz

100kHzInput,

+VA =5V,

f =1MSPS,

V

=5V

s

ref

THEORY OF OPERATION

ANALOG INPUT

ADS8329

ADS8330

SLAS516 – DECEMBER 2006

TYPICAL CHARACTERISTICS (continued)

Figure 49.

Figure 50.

The ADS8329/30 is a high-speed, low power, successive approximation register (SAR) analog-to-digital

converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which

inherently includes a sample/hold function.

The ADS8329/30 has an internal clock that is used to run the conversion but can also be programmed to run the

conversion based on the external serial clock, SCLK.

The ADS8329 has one analog input. The analog input is provided to two input pins: +IN and –IN. When a

conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a

conversion is in progress, both +IN and –IN inputs are disconnected from any internal function.

The ADS8330 has two inputs. Both inputs share the same common pin - COM. The negative input is the same

as the -IN pin for the ADS8329. The ADS8330 can be programmed to select a channel manually or can be

programmed into the auto channel select mode to sweep between channel 0 and 1 automatically.

When the converter enters hold mode, the voltage difference between the +IN and –IN inputs is captured on the

internal capacitor array. The voltage on the –IN input is limited between AGND – 0.2 V and AGND + 0.2 V,

allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a

The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input

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