LTC2440IGN datasheet(15/28 Pages) LINER

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LTC2440

sn2440, 2440fas

APPLICATIO S I FOR ATIO

Figure 5. External Serial Clock, Single Cycle Operation

EOC

BIT 31

SDO

BUSY

SCK

(EXTERNAL)

TEST EOC

SUB LSB

MSB

SIG

BIT 0

LSB

BIT 5

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

2440 F05

CONVERSION

Hi-Z

TEST EOC

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

VCC

BUSY

REF+

REF–

SCK

IN+

IN–

SDO

GND

EXT

1, 8, 9, 16

SDI

REFERENCE VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

µF

4.5V TO 5.5V

LTC2440

3-WIRE

SPI INTERFACE

200nV NOISE, 50/60Hz REJECTION

10-SPEED/RESOLUTION PROGRAMMABLE

µV NOISE, 880Hz OUTPUT RATE

VCC

EOC = 1 (BUSY = 1) while a conversion is in progress and

EOC = 0 (BUSY = 0) if the device is in the sleep state.

Independent of CS, the device automatically enters the low

power sleep state once the conversion is complete.

When the device is in the sleep state (EOC = 0), its

conversion result is held in an internal static shift regis-

ter. The device remains in the sleep state until the first

rising edge of SCK is seen. Data is shifted out the SDO pin

on each falling edge of SCK. This enables external circuitry

to latch the output on the rising edge of SCK. EOC can be

latched on the first rising edge of SCK and the last bit of

the conversion result can be latched on the 32nd rising

edge of SCK. On the 32nd falling edge of SCK, the device

begins a new conversion. SDO goes HIGH (EOC = 1) and

BUSY goes HIGH indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z

and BUSY monitored for the completion of a conversion.

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status on the SDO pin.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the fifth falling edge (SDI must

be properly loaded each cycle) and the 32nd falling edge

of SCK, see Figure 6. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 32-bits of output data, aborting an invalid conversion

cycle or synchronizing the start of a conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 7. CS

may be permanently tied to ground, simplifying the user

interface or isolation barrier. The external serial clock

mode is selected by tying EXT LOW.

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. Conversely, BUSY (Pin 15) may be used

to monitor the status of the conversion cycle. EOC or BUSY

may be used as an interrupt to an external controller

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