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9

S5933

32-Bit PCI “MatchMaker”

EWR#

t/s

External nv Memory Write Control. This pin is asserted during write operations involving

the external non-volatile memory. Data is presented on pins EQ[7:0] along with its address

on pins EA[15:0] throughout the entire assertion of EWR#. This pin is shared with the

serial external memory interface signal, SDA.

EQ[7:0]

t/s

External Memory Data Bus. These pins are used to directly connect with the data pins of

an external non-volatile memory. When a serial memory is connected to the S5933, the

pins EQ4, EQ5, EQ6, and EQ7 become reconfigured to provide signal pins for bus master-

ing control from the Add-On interface.

DQ[31:0]

t/s

Address/Data Bus. The 32 bit Add-On data bus. The DQMODE signal configures the bus

width for either 32 or 16 bits. All DQ[31:0] signals have an internal pull-up.

ADR[6:2}

in

Address [6:2]. These inputs select which S5933 register is to be read from or written to. To

be used in conjunction with SELECT#, BE[3:0]# and WR# or RD#. The following table

shows the register addresses.

ADR

[6

5

4

3

2]

Description

0

0

0

1

1

Add-On Incoming Mailbox Register

0

0

1

1

1

Add-On Outgoing Mailbox Register

0

1

0

1

0

Add-On Pass-Thru Address Register

0

1

0

1

1

Add-On Pass-Thru Data Register

0

1

1

0

1

Add-On Mailbox Status Register

0

1

1

1

0

Add-On Interrupt Control Register

0

1

1

1

1

Add-On Reset Control Register

1

0

0

0

0

Pass-Thru/FIFO Configuration Register

BE[2:0]#

in

Byte Enable [2:0]. Provides individual read/write byte enabling during register read or

write transactions. BE2# enables activity over DQ[23:16], BE1# enables DQ[15:8], and

BE0# enables DQ[7:0]. During read transactions, enables the output driver for each byte

lane; for write transactions, serves as an input enable to perform the write to each byte

lane.

BE3#/ADR1

in

Byte Enable 3/Address 1. BE3#, enables DQ[31:24] input drivers for writing data to regis-

ters identified by ADR[6:2] and enables DQ[31:24] output drivers to read registers identi-

fied by ADR[6:2]. To be used in conjunction with SELECT# and RD# or WR#. ADR1,

selects the upper or lower WORD of a DWORD when a 16 bit wide bus is selected. 1 =

lower, 0 = upper.

SELECT#

in

Select. Enables internal S5933 logic to decode WR#, RD# and ADR[6:2] when reading or

writing to any Add-On register.

WR#

in

Write Enable. Asserting this signal writes DQ bus data byte(s) selected by BE[3:0]# into

the S5933 register defined by SELECT# and ADR[6:2].

RD#

in

Read Enable. Asserting this signal drives data byte(s) selected by BE[3:0]# from the

S5933 register defined by SELECT# and ADR[6:2] onto the DQ bus.

MODE

in

DQ Mode. Defines the DQ bus width when accessing data using WR#, RD#, SELECT#

and ADR[6:2]#. Low = 32-bit wide DQ bus. High = 16-bit wide DQ bus. When high, the

signal BE3# is re-assigned to the ADR1 signal and only DQ[15:0] is active.

PTATN#

out

Pass-Thru Attention. Signals a decoded PCI to Pass-Thru region bus cycle. PTATN# is

generated to signal Add-On logic Pass-Thru data must be read from or written to the

S5933.