S5935QF datasheet(13/190 Pages) AMCC

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ARCHITECTURAL OVERVIEW

S5935

Add-On Pass-Thru Read Data

Add-On Pass-Thru Write Data

Address Latch

Add-On Pass-

Thru Address

Pass-Thru Operation

Pass-Thru operation executes PCI bus cycles in real

time with the Add-On bus. This allows the PCI bus to

directly read or write to Add-On resources. The S5935

allows the designer to declare up to four individual

Pass-Thru Regions. Each region may be defined as 8,

16-, or 32-bits wide, mapped into host memory or I/O

space and may be up to 512MB bytes in size. Figure 4

right shows a block diagram of the S5935 Pass-Thru

architecture.

Pass-Thru operations are performed in PCI target only

mode, making this data channel useful for converting

existing ISA or EISA designs over to the fast PCI

architecture. The Pass-Thru data channel utilizes sepa-

rate Add-On bus signal pins to reflect a PCI bus read or

write request. Add-On logic decodes these signals to

determine if it must read or write data to the S5935 to

satisfy the request. Information decoded includes PCI

request occurring, the byte lanes involved, the specific

Pass-Thru region accessed and if the request is a burst

or single-cycle access. All requested Pass-Thru ad-

dress and data information is passed via Add-On Op-

eration Registers.

Pass-Thru operation supports single PCI data cycles

and PCI data bursts. During PCI burst operations, the

S5935 is capable of transferring data at the full PCI

bandwidth. Should slower Add-On logic be implemented,

the S5935 automatically issues PCI bus waits or a Host

retry indication until the requested transfer is satisfied.

FIFO PCI Bus Mastering Operation

FIFO PCI Bus Master data transfers are processed by

one of two 8-DWORD FIFOs. The FIFO block diagram

is shown in Figure 5. The particular FIFO selected for a

data transfer is dependent only on the direction of data

flow and is completely transparent to the user. Internal

S5935 decode logic selects the FIFO that is dedicated

to transferring data to the other bus.

The way data is transferred by a FIFO, is determined by

Operation and Configuration Registers contained within

the S5935. A FIFO may be configured for either PCI or

Add-On initiated Bus Mastering with programmable

byte advance conditions, read vs. write priorities and

Add-On bus widths. Advance conditions allow the FIFO

to implement 8-, 16- or 32-bit bus widths. Configuring

the S5935 for Bus Master operation enables separate

address and data count registers, which are loaded with

the PCI memory address location and number of bytes

to be read or written. This is accomplished by either the

Host CPU or Add-On logic. Data can be transferred

between the two buses transparent to the PCI Host

processor, however, the Add-On logic is required to

service the S5935 Add-On Local bus. An indication of

transfer completion can be seen by polling a status

‘transfer count = 0’ interrupt to either bus.

Further FIFO configuration bits select 16, 32, or 64 bit

Endian conversion options for incoming and outgoing

data. Endian conversion allows an Add-On processor

and the host to transfer data in their native Endian

format. Other configuration bits determine if the Add-On

Local bus width is 8, 16 or 32 bits. 16-bit bus configura-

tions internally steer FIFO data from the upper 16 bits of

the DWORD and then to the lower 16-bits on alternate

accesses. FIFO pointers are then updated when appro-

priate bytes are accessed. Other methods are available

for 8-bit or 16-bit Add-Ons.

Efficient FIFO management configuration schemes

unique to the AMCC S5935 specify how full or empty a

FIFO must be before it requests the PCI Local bus.

These criteria include bus requests when any of the 8

DWORDs are empty, or when four or more DWORDs

are empty. This allows the designer to control how often

the S5935 requests the bus. The S5935 always at-

tempts to perform burst operations to empty or fill the

FIFOs. Further FIFO capabilities over the standard

access. This is provided through separate access pins

on the S5935. Other status output pins allow for easily

cascading external FIFOs to the Add-On design.

Figure 4.

S5935QF Datasheet(PDF) 13 Page - Applied Micro Circuits Corporation

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