S5935QF datasheet(4/190 Pages) AMCC

4 / 190 page

Minimum Grant Register (MINGNT) ................................................................................................... 3-42

Maximum Latency Register (MAXLAT) ............................................................................................... 3-43

4. PCI BUS OPERATION REGISTERS ...................................................................................................... 4-45

Outgoing Mailbox Registers (OMB) .................................................................................................... 4-46

Incoming Mailbox Registers (IMB) ...................................................................................................... 4-46

FIFO Register Port (FIFO) .................................................................................................................. 4-46

PCI Controlled Bus Master Write Address Register (MWAR) ............................................................. 4-47

PCI Controlled Bus Master Write Transfer Count Register (MWTC) .................................................. 4-48

PCI Controlled Bus Master Read Address Register (MRAR) ............................................................. 4-49

PCI Controlled Bus Master Read Transfer Count Register (MRTC) ................................................... 4-50

Mailbox Empty Full/Status Register (MBEF) ....................................................................................... 4-51

Interrupt Control/Status Register (INTCSR) ........................................................................................ 4-53

Master Control/Status Register (MCSR) ............................................................................................. 4-57

5. ADD-ON BUS OPERATION REGISTERS ............................................................................................. 5-61

Add-On Incoming Mailbox Registers (AIMBx) .................................................................................... 5-62

Add-On Outgoing Mailbox Registers (AOMBx) ................................................................................... 5-62

Add-On FIFO Register Port (AFIFO) .................................................................................................. 5-62

Add-On Controlled Bus Master Write Address Register (MWAR) ....................................................... 5-63

Add-On Pass-Thru Address Register (APTA) ..................................................................................... 5-64

Add-On Pass-Thru Data Register (APTD) .......................................................................................... 5-64

Add-On Controlled Bus Master Read Address Register (MRAR) ....................................................... 5-65

Add-On Empty/Full Status Register (AMBEF) .................................................................................... 5-66

Add-On Interrupt Control/Status Register (AINT) ............................................................................... 5-68

Add-On General Control/Status Register (AGCSTS) ......................................................................... 5-71

Add-On Controlled Bus Master Write Transfer Count Register (MWTC) ............................................ 5-74

Add-On Controlled Bus Master Read Transfer Count Register (MRTC) ............................................ 5-75

6. INITIALIZATION ..................................................................................................................................... 6-77

PCI Reset ............................................................................................................................................ 6-77

Loading From Byte-wide nv Memories ............................................................................................... 6-77

Loading From Serial nv Memories ...................................................................................................... 6-78

PCI Bus Configuration Cycles ............................................................................................................. 6-80

Expansion BIOS ROMs ...................................................................................................................... 6-82

7. PCI BUS INTERFACE ............................................................................................................................ 7-85

PCI Bus Transactions ......................................................................................................................... 7-86

PCI Burst Transfers ................................................................................................................. 7-86

PCI Read Transfers ................................................................................................................. 7-88

PCI Write Transfers ................................................................................................................. 7-89

Master-Initiated Termination .................................................................................................... 7-89

Normal Cycle Completion ........................................................................................................ 7-89

Initiator Preemption ................................................................................................................. 7-90

Master Abort ............................................................................................................................ 7-91

Target-Initiated Termination ..................................................................................................... 7-91

S5935QF Datasheet(PDF) 4 Page - Applied Micro Circuits Corporation

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