Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

qn = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care; ↑ = LOW-to-HIGH clock transition.

Input

Output

Operating

modes

MR

CP

CEP

CET

PE

Dn

Qn

TC

Reset (clear)

L

X

X

X

X

X

L

L

H

↑

X

X

l

l

L

L

Parallel load

H

↑

X

X

l

h

H

[1]

Count

H

↑

h

h

h

X

count

[1]

H

X

l

X

h

X

qn

[1]

Hold (do nothing)

H

X

X

l

h

X

qn

L

[1] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)

aaa-012187

0

15

14

13

5

6

7

12

1

2

3

4

11

10

9

8

Fig. 7. State diagram

74HC161

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 5 — 16 March 2021

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