Nexperia

74HC161

Presettable synchronous 4-bit binary counter; asynchronous reset

25 °C

-40 °C to +85 °C -40 °C to +125 °C

Symbol Parameter

Conditions

Min Typ Max

Min

Max

Min

Max

Unit

MR to CP; see Fig. 11

VCC = 2.0 V

100

19

-

125

-

150

-

ns

VCC = 4.5 V

20

7

-

25

-

30

-

ns

trec

recovery time

VCC = 6.0 V

17

6

-

21

-

26

-

ns

Dn to CP; see Fig. 12

VCC = 2.0 V

80

25

-

100

-

120

-

ns

VCC = 4.5 V

16

9

-

20

-

24

-

ns

VCC = 6.0 V

14

7

-

17

-

20

-

ns

PE to CP; see Fig. 12

VCC = 2.0 V

100

30

-

125

-

150

-

ns

VCC = 4.5 V

20

11

-

25

-

30

-

ns

VCC = 6.0 V

17

9

-

21

-

26

-

ns

CEP, CET to CP; see Fig. 13

VCC = 2.0 V

170

47

-

215

-

255

-

ns

VCC = 4.5 V

34

17

-

43

-

51

-

ns

tsu

set-up time

VCC = 6.0 V

29

14

-

37

-

43

-

ns

Dn, PE, CEP, CET to CP;

see Fig. 12 and Fig. 13

VCC = 2.0 V

0

-14

-

0

-

0

-

ns

VCC = 4.5 V

0

-5

-

0

-

0

-

ns

th

hold time

VCC = 6.0 V

0

-4

-

0

-

0

-

ns

CP; see Fig. 9

VCC = 2.0 V

4.6

13

-

3.6

-

3.0

-

MHz

VCC = 4.5 V

23

40

-

18

-

15

-

MHz

VCC = 5.0 V; CL = 15 pF

-

44

-

-

-

-

-

MHz

fmax

maximum

frequency

VCC = 6.0 V

27

48

-

21

-

18

-

MHz

CPD

power

dissipation

capacitance

VI = GND to VCC; VCC = 5 V;

fi = 1 MHz

[3]

-

33

-

-

-

-

-

pF

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in μW):

PD = CPD x VCC 2 x fi × N + ∑(CL x VCC 2 x fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL x VCC 2 x fo) = sum of outputs.

74HC161

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 5 — 16 March 2021

9 / 17