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CS5535 Datasheet(PDF) 190 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CS5535
Description  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5535 Datasheet(HTML) 190 Page - National Semiconductor (TI)

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190
Revision 0.8
GLIU Register Descriptions (Continued)
5.1.1.3
GeodeLink Device SMI MSR (GLIU_GLD_MSR_SMI)
The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 0. Reading the FLAG bit returns
the value; writing 1 clears the flag; writing 0 has no effect. (See Section 3.8.3 "MSR Address 2: SMI Control" on page 67 for
further SMI and ASMI generation details.)
MSR Address
51010002h
Type
R/W
Reset Value
00000000_00000001h
GLIU_GLD_MSR_SMI Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
GLIU_GLD_MSR_SMI Bit Descriptions
Bit
Name
Description
63:36
RSVD
Reserved. Write as read.
35
STATCNT2_
ASMI_FLAG
Statistic Counter 2 ASMI Flag. If high, records that an ASMI was generated due to a
Statistic Counter 2 (MSR 510100A8h) event. Write 1 to clear; writing 0 has no effect.
STATCNT2_ASMI_EN (bit 3) must be low to generate ASMI and set flag.
34
STATCNT1_
ASMI_FLAG
Statistic Counter 1 ASMI Flag. If high, records that an ASMI was generated due to a
Statistic Counter 1 (MSR 510100A4h) event. Write 1 to clear; writing 0 has no effect.
STATCNT1_ASMI_EN (bit 2) must be low to generate ASMI and set flag.
33
STATCNT0_
ASMI_FLAG
Statistic Counter 0 SMI Flag. If high, records that an ASMI was generated due to a Sta-
tistic Counter 0 (MSR 510100A0h) event. Write 1 to clear; writing 0 has no effect.
STATCNT0_ASMI_EN (bit 1) must be low to generate ASMI and set flag.
32
SSMI_FLAG
SSMI Flag. If high, records that an SSMI was generated due to a received event. Event
sources are:
• Illegal request type to GLIU (Port 0), meaning anything other than MSR read/write,
debug request, and null.
• A self-referencing packet (i.e., a packet sent to the GLIU that finds its destination port
is the source port).
• The destination of the packet is to a port where the GLIU slave for that port has been
disabled.
• Trap on a descriptor with device port set to 0. This is the typical operational use of this
bit. The data returned with such a trap is the value 0.
Write 1 to clear; writing 0 has no effect. SSMI_EN (bit 0) must be low to generate SSMI
and set flag.
31:4
RSVD
Reserved. Write as read.



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