CS5535 datasheet(203/555 Pages) NSC

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GLIU Register Descriptions (Continued)

5.1.3.12

Descriptor Statistic Counters (GLIU_STATISTIC_CNT[x])

Descriptor Statistic Counter 0 (GLIU_STATISTIC_CNT0)

Descriptor Statistic Counter 1 (GLIU_STATISTIC_CNT1)

Descriptor Statistic Counter 2 (GLIU_STATISTIC_CNT2)

These registers work in conjunction with the GLIU_STATISTIC_MASK[x] and the GLIU_STATISTIC_ACTION[x] registers.

The

counters

count

‘hits’

the

P2D

and

IOD

descriptors.

The

counter

behaves

setup

the

GLIU_STATISTIC_ACTION[x] register.

MSR Address

510100A0h

Type

Reset Value

00000000_00000000h

MSR Address

510100A4h

Type

Reset Value

00000000_00000000h

MSR Address

510100A8h

Type

Reset Value

00000000_00000000h

GLIU_STATISTIC_CNT[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

LOAD_VAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

CNT

GLIU_STATISTIC_CNT[x] Bit Descriptions

Bit

Name

Description

63:32

LOAD_VAL

Counter Load Value. A value loaded here will be used as the initial Statistics Counter

value when a LOAD action occurs or is commanded.

31:0

CNT

Counter Value. These bits provide the current counter value when read.

CS5535 Datasheet(PDF) 203 Page - National Semiconductor (TI)

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