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CS5535 Datasheet(PDF) 222 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 222 Page - National Semiconductor (TI) |
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222 / 555 page ![]() www.national.com 222 Revision 0.8 GLPCI_SB Register Descriptions (Continued) 1IE IB I/O Enable. Enable handling of in-bound I/O transactions from PCI. When set to 1 the PCI interface accepts all in-bound I/O transactions from PCI. This mode is only intended for design verification purposes. When cleared to 0 no in-bound I/O transactions are accepted. 0ME IB Memory Enable. Enable handling of in-bound memory access transaction from PCI. When cleared to 0, the PCI interface does not accept any in-bound memory transactions from the PCI bus. GLPCI_CTRL Bit Descriptions (Continued) Bit Name IB/OB Description |
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