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CS5535 Datasheet(PDF) 244 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 244 Page - National Semiconductor (TI) |
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244 / 555 page  www.national.com 244 Revision 0.8 ACC Register Descriptions (Continued) 5.3.2.8 Audio Bus Master 0-7 IRQ Status Registers (ACC_BM[x]_STATUS) Bus Master 0 IRQ Status (ACC_BM0_STATUS) Bus Master 1 IRQ Status (ACC_BM1_STATUS) Bus Master 2 IRQ Status (ACC_BM2_STATUS) Bus Master 3 IRQ Status (ACC_BM3_STATUS) Bus Master 4 IRQ Status (ACC_BM4_STATUS) Bus Master 5 IRQ Status (ACC_BM5_STATUS) Bus Master 6 IRQ Status (ACC_BM6_STATUS) Bus Master 7 IRQ Status (ACC_BM7_STATUS) ACC I/O Offset 21h Type RC Reset Value 00h ACC I/O Offset 29h Type RC Reset Value 00h ACC I/O Offset 31h Type RC Reset Value 00h ACC I/O Offset 39h Type RC Reset Value 00h ACC I/O Offset 41h Type RC Reset Value 00h ACC I/O Offset 49h Type RC Reset Value 00h ACC I/O Offset 51h Type RC Reset Value 00h ACC I/O Offset 59h Type RC Reset Value 00h ACC_BM[x]_STATUS Register Map 76 54 32 10 RSVD BM_EOP_ERR EOP ACC_BM[x]_STATUS Bit Descriptions Bit Name Description 7:2 RSVD Reserved. Reads return 0 1 BM_EOP_ERR Bus Master Error. If this bit is set, it indicates that hardware encountered a second EOP before software cleared the first EOP. If hardware encounters a second EOP (end of page) before software clears the first EOP, it causes the bus master to pause until this register is read to clear the error. Read to clear. 0EOP End of Page. If this bit is set, it indicates the bus master transferred data that is marked by the EOP bit in the PRD table (bit 30). Read to clear. |
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