CS5535 datasheet(259/555 Pages) NSC

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ATAC Register Descriptions (Continued)

5.4.3.2

Bus Master 0 Status - Primary (ATAC_BM0_STS_PRIM)

0BMCTL

Bus Master Control. Controls the state of the bus master.

0: Disable master.

1: Enable master.

Bus master operations can be halted by setting bit 0 to 0. Once an operation has been

halted, it can not be resumed. If bit 0 is set to 0 while a bus master operation is active,

the command is aborted and the data transferred from the drive is discarded. This bit

should be reset after completion of data transfer.

ATAC I/O Address 02h

Type

R/W

Reset Value

00h

ATAC_BM0_STS_PRIM Register Map

MODE

D1DMA

D0DMA

RSVD

BMINT

BMERR

BMSTS

ATAC_BM0_STS_PRIM Bit Descriptions

Bit

Name

Description

MODE (RO)

Simplex Mode (Read Only). Can both the primary and secondary channel operate

independently?

0: Yes.

1: No (simplex mode).

6D1DMA

Drive 1 DMA Capable. Allows Drive 1 to be capable of DMA transfers.

0: Disable.

1: Enable.

5D0DMA

Drive 0 DMA Capable. Allows Drive 0 to be capable of DMA transfers.

0: Disable.

1: Enable.

4:3

RSVD

Reserved: Set to 0. Must return 0 on reads.

2BMINT

Bus Master Interrupt. Has the bus master detected an interrupt?

0: No.

1: Yes.

Write 1 to clear.

1BMERR

Bus Master Error. Has the bus master detected an error during data transfer? (This bit

is set by a write access to MSR 51300024h.)

0: No.

1: Yes.

Write 1 to clear.

0BMSTS (RO)

Bus Master Status (Read Only). Is the bus master active?

0: No.

1: Yes.

ATAC_BM0_CMD_PRIM Bit Descriptions

Bit

Name

Description

CS5535 Datasheet(PDF) 259 Page - National Semiconductor (TI)

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