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CS5535 Datasheet(PDF) 386 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 386 Page - National Semiconductor (TI) |
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386 / 555 page ![]() www.national.com 386 Revision 0.8 UART/IR Controller Register Descriptions (Continued) 5.12.5.5 TX_FIFO Current Level Register (TXFLV) TXFLV returns the number of bytes in the TX_FIFO. 5:4 PRESL[1:0] Prescaler Select. The prescaler divides the 24 MHz input clock frequency to provide the clock for the baud generator. 00: 13 (Default) 01: 1.625 10: Reserved 11: 1.0 3:2 RF_SIZ[1:0] RX_FIFO Levels Select. These bits select the number of levels for the RX_FIFO. They are effective only when the FIFOs are enabled. (FCR bit 0 = 1.) 00: 16 (Default) 01: 32 1x: Reserved 1:0 TF_SIZ[1:0] TX_FIFO Levels Select. These bits select the number of levels for the TX_FIFO. They are effective only when the FIFOs are enabled. (FCR bit 0 = 1.) 00: 16 (Default) 01: 32 1x: Reserved I/O Offset 06h Type RO Reset Value 00h TXFLV Register Map 76 54 32 10 RSVD TFL[5:0] TXFLV Bit Descriptions Bit Name Description 7:6 RSVD Reserved. Returns 0. 5:0 TFL[5:0] Number of Bytes in TX_FIFO. These bits specify the number of bytes in the TX_FIFO. Note: The contents of TXFLV and RXFLV are not frozen during CPU reads. Therefore, invalid data could be returned if the CPU reads these registers during normal transmitter and receiver operation. To obtain correct data, the software should perform three consecutive reads and then take the data from the second read if the first and second reads yield the same result. It can also be taken from the third read if the first and second reads yield different results. EXCR2 Bit Descriptions (Continued) Bit Name Description |
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