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CS5535 Datasheet(PDF) 466 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 466 Page - National Semiconductor (TI) |
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466 / 555 page  www.national.com 466 Revision 0.8 5.17 MULTI-FUNCTION GENERAL PURPOSE TIMER REGISTER DESCRIPTIONS The registers for the Multi-Function General Purpose Timer (MFGPT) are divided into three sets: • Standard GeodeLink Device MSRs (Shared with DIVIL, see Section 5.6.1 on page 299.) • MFGPT Specific MSRs • MFGPT Native Registers. The MSRs are accessed via the RDMSR and WRMSR pro- cessor instructions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. All MSRs are 64 bits, however, the MFGPT Specific MSRs (summarized in Table 5-64) are called out as 32 bits. The MFGPT module treats writes to the upper 32 bits (i.e., bits [63:32]) of the 64-bit MSRs as don’t cares and always returns 0 on these bits. The Native registers associated with the MFGPT (summa- rized in Table 5-65) are accessed via a Base Address Reg- ister, MSR_LBAR_MFGPT (MSR 5140000Dh), as I/O Offsets. (See Section 5.6.2.6 on page 311 for bit descrip- tions of the Base Address Register.) The reference column in the summary tables point to the page where the register maps and bit descriptions are listed. Table 5-64. MFGPT Specific MSRs Summary MSR Address Type Register Name Reset Value Reference 51400028h R/W MFGPT IRQ Mask (MFGPT_IRQ) 00000000h Page 467 51400029h R/W MFGPT NMI and Reset Mask (MFGPT_NR) 00000000h Page 469 5140002Ah R/W MFGPT Reserved (MFGPT_RSVD) 00000000h Page 471 5140002Bh WO MFGPT Clear Setup Test (MFGPT_SETUP) 00000000h Page 471 Table 5-65. MFGPT Native Registers Summary MFGPT I/O Offset Type Width (Bits) Register Name Reset Value Reference 00h R/W 16 MFGPT0 Comparator 1 (MFGPT0_CMP1) 0000h Page 472 02h R/W 16 MFGPT0 Comparator 2 (MFGPT0_CMP2) 0000h Page 473 04h R/W 16 MFGPT0 Up Counter (MFGPT0_CNT) 0000h Page 474 06h R/W 16 MFPGT0 Setup (MFGPT0_SETUP) 0000h Page 475 08h R/W 16 MFGPT1 Comparator 1 (MFGPT1_CMP1) 0000h Page 472 0Ah R/W 16 MFGPT1 Comparator 2 (MFGPT1_CMP2) 0000h Page 473 0Ch R/W 16 MFGPT1 Up Counter (MFGPT1_CNT) 0000h Page 474 0Eh R/W 16 MFPGT1 Setup (MFGPT1_SETUP) 0000h Page 475 10h R/W 16 MFGPT2 Comparator 1 (MFGPT2_CMP1) 0000h Page 472 12h R/W 16 MFGPT2 Comparator 2 (MFGPT2_CMP2) 0000h Page 473 14h R/W 16 MFGPT2 Up Counter (MFGPT2_CNT) 0000h Page 474 16h R/W 16 MFPGT2 Setup (MFGPT2_SETUP) 0000h Page 475 18h R/W 16 MFGPT3 Comparator 1 (MFGPT3_CMP1) 0000h Page 472 1Ah R/W 16 MFGPT3 Comparator 2 (MFGPT3_CMP2) 0000h Page 473 1Ch R/W 16 MFGPT3 Up Counter (MFGPT3_CNT) 0000h Page 474 1Eh R/W 16 MFPGT3 Setup (MFGPT3_SETUP) 0000h Page 475 20h R/W 16 MFGPT4 Comparator 1 (MFGPT4_CMP1) 0000h Page 472 22h R/W 16 MFGPT4 Comparator 2 (MFGPT4_CMP2) 0000h Page 473 24h R/W 16 MFGPT4 Up Counter (MFGPT4_CNT) 0000h Page 474 26h R/W 16 MFPGT4 Setup (MFGPT4_SETUP) 0000h Page 475 28h R/W 16 MFGPT5 Comparator 1 (MFGPT5_CMP1) 0000h Page 472 |
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