CS5535 datasheet(105/555 Pages) NSC

105 / 555 page

Revision 0.8

105

www.national.com

PIC Functional Description (Continued)

4.8.2

Extended PIC (XPIC)

For each of 16 input IGs of four signals each (except IG0

and IG2 with two signals each), XPIC provides a four input

“OR”. Thus, 16 outputs are formed. A software readable

XPIC Input Request Register (XIRR) is available to read

the status of the 64 inputs. Outputs [0:1] and [3:15] are

connected directly to the corresponding inputs on LPIC.

Output 2 can be used as an ASMI.

4.8.3

Legacy PIC (LPIC)

The LPIC consists of two 8259A compatible Programmable

Interrupt Controllers (PICs) connected in Cascade mode

through interrupt signal two (see Figure 4-19). LPIC con-

tains mechanisms to:

Mask any of the 15 inputs via an Interrupt Mask Regis-

ter (IMR).

Determine the input request status via an Interrupt

Request Register (IRR).

Generate an interrupt request (INTR) to the processor

when any of the unmasked requests are asserted.

Provide an interrupt vector to the processor as part of

an interrupt acknowledge operation based on request

priorities.

Determine which requests are acknowledged but not

yet fully serviced, via an In-Service Register (ISR).

In addition to the above 8259A features, there are two reg-

isters to control edge/level mode for each of the interrupt

inputs as well as shadow registers to obtain the values of

legacy 8259A registers that have not been historically

readable.

Figure 4-19. Cascading 8259As for LPIC

Table 4-14. IRQ Map - Unrestricted Sources Z

Unrestricted Z

Source

Comment

Input 0

MFGPT_Comp_1A

OR of MFGPT_Comp_1 0 and 4.

Input 1

MFGPT_Comp_1B

OR of MFGPT_Comp_1 1 and 5.

Input 2

MFGPT_Comp_1C

OR of MFGPT_Comp_1 2 and 6.

Input 3

MFGPT_Comp_1D

OR of MFGPT_Comp_1 3 and 7.

Input 4

MFGPT_Comp_2A

OR of MFGPT_Comp_2 0 and 4.

Input 5

MFGPT_Comp_2B

OR of MFGPT_Comp_2 1 and 5.

Input 6

MFGPT_Comp_2C

OR of MFGPT_Comp_2 2 and 6.

Input 7

MFGPT_Comp_2D

OR of MFGPT_Comp_2 3 and 7.

Input 8

GPIO Interrupt 0