CS5535 datasheet(121/555 Pages) NSC

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SMB Controller Functional Description (Continued)

Bus Idle Error Recovery

When a request to become the active bus master or a

restart operation fails, SMBST.BER is set to indicate the

error. In some cases, both the device and the other device

may identify the failure and leave the bus idle. In this case,

the START sequence may be incomplete and the bus may

remain deadlocked.

To recover from deadlock, use the following sequence:

Clear SMBST.BER and SMBCST.BB.

Wait for a time-out period to check that there is no

other active master on the bus (i.e., SMBCST.BB

remains cleared).

Disable, and re-enable the SMB Controller to put it in

the non-addressed slave mode. This completely resets

the functional block.

At this point, some of the slaves may not identify the bus

error. To recover, the SMB Controller becomes the bus

master: it asserts a START condition, sends an address

byte, then asserts a STOP condition that synchronizes all

the slaves.

4.10.1.7 Slave Mode

A slave device waits in Idle mode for a master to initiate a

bus transaction. Whenever the SMB Controller is enabled

and it is not acting as a master (i.e., SMBST.MASTER is

cleared), it acts as a slave device.

Once a START condition on the bus is detected, the device

checks whether the address sent by the current master

matches either:

• The SMBADDR.ADDR value if SMBADDR.SAEN = 1, or

• The general call address if SMBCTL1.GCMEN = 1.

This match is checked even when SMBST.MASTER is set.

If a bus conflict (on SDA or SCL) is detected, SMBST.BER

is set, SMBST.MASTER is cleared and the device contin-

ues to search the received message for a match.

If an address match or a global match is detected:

The device asserts its SDA line during the acknowl-

edge cycle.

SMBCST.MATCH and SMBST.NMATCH are set. If

SMBST.XMIT

(i.e.,

slave

transmit

mode)

SMBST.SDAST is set to indicate that the buffer is

empty.

If SMBCTL1.INTEN is set, an interrupt is generated if

both SMBCTL1.INTEN and SMBCTL1.NMINTE are

set.

The software then reads SMBST.XMIT to identify the

direction requested by the master device. It clears

SMBST.NMATCH so future byte transfers are identi-

fied as data bytes.

Slave Receive and Transmit

Slave receive and transmit are performed after a match is

detected and the data transfer direction is identified. After a

byte transfer, the SMB Controller extends the acknowledge

clock until the software reads or writes the SMBSDA regis-

ter. The receive and transmit sequences are identical to

those used in the master routine.

Slave Bus Stall

When operating as a slave, the device stalls the bus by

extending the first clock cycle of a transaction in the follow-

ing cases:

• SMBST.SDAST is set.

• SMBST.NMATCH and SMBCTL1.NMINTE are set.

Slave Error Detection

The SMB Controller detects an illegal START and STOP

conditions on the bus (i.e., a START or STOP condition

within the data transfer or the acknowledge cycle). When

this occurs, SMBST.BER is set and SMBCST.MATCH and

SMBCST.GMATCH are cleared, setting the SMB Controller

as an unaddressed slave.

CS5535 Datasheet(PDF) 121 Page - National Semiconductor (TI)

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