CS5535 datasheet(136/555 Pages) NSC

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LPC Port Functional Description (Continued)

When the host is driving SYNC, it may insert a very large

number of wait-states depending on PCI latencies. The

peripheral must not assume any timeouts.

SYNC Error Indication: A peripheral can report an error via

the LAD[3:0] = 1010b encoding. If the host was reading

data from a peripheral, the data will still be transferred in

the next two nibbles, even though this data is invalid, the

peripheral must transfer it. If the host was writing, data had

already been transferred.

In DMA if it was a multiple byte cycle, an error SYNC termi-

nates the cycle.

For more info on SYNC timeout and SYNC error details,

refer to the LPC Specification.

Table 4-23. Cycle Field Definitions: Target Memory, I/O, and DMA

Field

# Clocks

Comment

START

Start of Cycle. 0000b indicates a start of a cycle.

CYCTYP

Cycle Type. Indicates the type of cycle.

Bits [3:0]

Definition

000x

I/O Read

001x

I/O Write

010x

Memory Read

011x

Memory Write

100x

DMA Read

101x

DMA Write

1100

Reserved

1101

FWH Read

1110

FWH Write

1111

Reserved

CHANNEL

Channel #. Used only for DMA cycles to indicate channel number being granted. The LAD[2:0]

bits indicate the channel number being granted, and LAD[3] indicates the TC bit. The encoding

on LAD[2:0] for channel number is as follows:

LAD[2:0]

Definition

000

I/O Read

001

I/O Write

010

Memory Read

011

Memory Write

100-111

Reserved

Only 8-bit channels are supported.

TAR

Turn-Around. The last component driving LAD[3:0] will drive it high during the first clock and

TRI-STATE during the second clock.

SIZE

Size of Transfer. Used only for DMA cycles. Bits [3:0] are reserved and must be ignored by the

peripheral.

LAD[1:0]

Definition

8-Bit

01-11

Reserved

Only 8-bit is supported for all transfers.

DATA

1 Byte

DMA: 1 Byte

Data Phase. The data byte is transferred with the least significant nibble first (D[3:0] on

LAD[3:0], then D[7:4] on LAD[3:0]).

DMA. The data byte is transferred with the least significant nibble first (D[3:0] on LAD[3:0], then

D[7:4] on LAD[3:0]). Only one byte data transfer is supported.

ADDR

8 for Memory,

4 for I/O

Address Phase. Address is 32-bit for memory, 16-bit for I/O. It is transferred most significant

nibble first.

DMA cycles do not use the ADDR field.

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