CS5535 datasheet(142/555 Pages) NSC

142 / 555 page

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142

Revision 0.8

LPC Port Functional Description (Continued)

Figure 4-46. FWH Write Cycle

Table 4-27. FWH Read Cycle

Signal

Clock

Cycle

LAD[3:0]

Peripheral

I/O

Description

START

1101b

On the rising edge of CLK with LFRAME# low, the contents of

LAD[3:0] indicate the start of an FWH cycle.

IDSEL

0000

Indicates which FWH peripheral is selected. The value on the

LAD[3:0] is compared to the IDSEL strapping on the FWH device

pins to select which device is being addressed.

Note: From Intel 82802 Specification - the boot device must have

an ID (determined by ID strapping pins ID[3:0]) of 0. It is advisable

that subsequent devices use incremental numbering.

ADDR

xxxx

A 28-bit address phase is transferred starting with the most signifi-

cant nibble first.

MSIZE

0000b

Always 0000b (single byte transfer).

TAR

1111b

The LPC host drives LAD[3:0] to 1111b to indicate a turnaround

cycle.

TAR

1111b

(float)

The FWH device takes control of LAD[3:0] during this cycle.

WSYNC

0101b

The FWH device drives LAD[3:0] to 0101b (short wait-sync) for two

clock cycles, indicating that the data is not yet available.

RSYNC

0000b

The FWH device drives LAD[3:0] to 0000b, indicating that data will

be available during the next clock cycle.

DATA

xxxx

Data transfer is two cycles, starting with least significant nibble.

TAR

1111b

The FWH device drives LAD[3:0] to 1111b, to indicate a turnaround

cycle.

TAR

1111b

(float)

N/A

The FWH device floats its output and the LPC host takes control of

LAD[3:0].

LCLK

LFRAME#

LAD[3:0]

(FWH0-FWH3)

Number of Clock Cycles

START

IDSEL

ADDR

MSIZE

TAR

SYNC

DATA

TAR

(FWH4)

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