Nexperia

74ALVC125

Quad buffer/line driver; 3-state

4. Functional diagram

mna228

1A

1Y

2

1

3

1OE

2A

2Y

5

4

6

2OE

3A

3Y

9

10

8

3OE

4A

4Y

12

13

11

4OE

Fig. 1. Logic symbol

mna229

1

EN1

1

3

2

4

6

5

10

8

9

13

11

12

Fig. 2. IEC logic symbol

mna227

nOE

nA

nY

Fig. 3. Logic diagram (one buffer)

5. Pinning information

5.1. Pinning

74ALVC125

1OE

VCC

1A

4OE

1Y

4A

2OE

4Y

2A

3OE

2Y

3A

GND

3Y

001aah089

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

001aah090

74ALVC125

Transparent top view

GND(1)

2Y

3A

2A

3OE

2OE

4Y

1Y

4A

1A

4OE

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND

Fig. 5. Pin configuration SOT762-1 (DHVQFN14)

74ALVC125

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 4 — 30 April 2021

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