Data Sheet

ADXL358

APPLICATIONS INFORMATION

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Rev. 0 | 12 of 16

Figure 26 shows the ADXL358 application circuit. The analog

outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V analog

voltage from the V1P8ANA pin. V1P8ANA can be powered with an

on-chip LDO regulator that is powered from VSUPPLY. V1P8ANA

can also be supplied externally by forcing VSUPPLY to VSS, which

disables the LDO regulator. Due to the ratiometric response, the

analog output requires referencing to the V1P8ANA supply when

digitizing to achieve the inherent noise and offset performance of

the ADXL358. The 0 g bias output is nominally equal to V1P8ANA/2.

The recommended option is to use the ADXL358 with a ratiometric

analog-to-digital converter (ADC), for example, the Analog Devices,

Inc., AD7682, and V1P8ANA providing the voltage reference. This

configuration results in self cancellation of errors due to minor

supply variations.

Figure 26. ADXL358 Application Circuit

The ADXL358 outputs two forms of filtering: internal antialiasing

filtering with a cutoff frequency of approximately 1.5 kHz, and

external filtering. The external filter uses a fixed, on-chip, 32

kΩ resistance in series with each output in conjunction with the

external capacitors to implement the low-pass filter antialiasing

and noise reduction prior to the external ADC. The antialias filter

cutoff frequency must be significantly higher than the desired signal

bandwidth. If the antialias filter corner is too low, ratiometricity can

degrade where the signal attenuation is different from the reference

attenuation.

AXES OF ACCELERATION SENSITIVITY

Figure 27 shows the axes of acceleration sensitivity. Note that the

output voltage increases when accelerated along the sensitive axis.

Figure 27. Axes of Acceleration Sensitivity

POWER SEQUENCING

There are two methods for applying power to the device. Typically,

internal LDO regulators generate the 1.8 V power for the analog

and digital supplies, V1P8ANA and V1P8DIG, respectively. Optionally,

the internal LDO regulators can be disabled, and V1P8ANA and

V1P8DIG can be driven by external 1.8 V supplies.

When using the internal LDO regulators, connect VSUPPLY to a

voltage source between 2.25 V and 3.6 V. In this case, the recom-

mended power sequence is to apply power to VDDIO, followed by

applying power to VSUPPLY approximately 10 µs after. If necessary,

VSUPPLY and VDDIO can be powered from the same voltage source

so that both are powered at the same time. However, VSUPPLY

cannot be powered before VDDIO.

To disable the internal LDO regulators, tie VSUPPLY to ground and

use external 1.8 V supplies to power V1P8ANA and V1P8DIG. V1P8ANA

and V1P8DIG must have the same voltage level. The maximum

acceptable tolerance between the external V1P8ANA and V1P8DIG

voltage levels is 50 mV. When bypassing the LDO regulators, the

recommended power sequence is to apply power to VDDIO, followed

by applying power to V1P8DIG approximately 10 µs after, and then

applying power to V1P8ANA approximately 10 µs after. If necessary,

V1P8DIG and VDDIO can be powered from the same external 1.8

V supply, which can also be tied to V1P8ANA with proper isolation

so that all are powered at the same time. In this instance, proper

decoupling and low frequency isolation are important to maintain

the noise performance of the sensor.