MIC4606 datasheet(17/40 Pages) MICROCHIP

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DS20005604D-page 17

MIC4606

5.0

FUNCTIONAL DIAGRAM

For xHO to be high, the xHI must be high and the xLO

must be low. xHO going high is delayed by xLO falling

below 1.9V. The xHI and xLI inputs must not rise at the

same time to prevent a glitch from occurring on the out-

put. A minimum 50 ns delay between both inputs is

recommended.

xLO is turned off very quickly on the xLI falling edge.

xLO going high is delayed by the longer of the 35 ns

delay of the xHO control signal going “off” or the RS

latch being set.

The latch is set by the quicker of either the falling edge

of xHS or an xLI gated delay of 250 ns. The latch is

present to lock out xLO bounce due to ringing on xHS.

If xHS never adequately falls due to the absence of or

the presence of a very weak external pull-down on

xHS, the gated delay of 250 ns at xLI will set the latch,

allowing xLO to transition high. This, in turn, allows the

xLI start-up pulse to charge the bootstrap capacitor if

the load inductor current is very low and xHS is

uncontrolled. The latch is reset by the xLI falling edge.

There is one external enable pin that controls both

phases.

FIGURE 5-1:

MIC4606 xPhase Top-Level Block Diagram.

FIGURE 5-2:

Input Logic Block in Figure 5-1.

BIAS

REF

INPUT

LOGIC

( SEE DIAGRAM

BELOW)

-2

ONLY

-1

ONLY

-1 HI

-2 PWM

-1 LI

-2 NC

VDD

xHB

xHO

xHS

xLO

EDGE

*COMMON TO

BOTH PHASES

UVLO

LEVEL

SHIFT

1.9V

35 ns

DELAY

250 ns

DELAY

2.2V

SECTION

FF RESET

SECTION

AND INPUT

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