 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD6708 Datasheet(PDF) 21 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
UPD6708 Datasheet(HTML) 21 Page - Renesas Technology Corp |
|
|
21 / 74 page  19 µPD6708 2.5 Bit Format The IEBus communication frame bit format (concept) is shown in Figure 2-4. Figure 2-4. IEBus Bit Format (Concept) Logic “1”: Potential difference between bus lines (BUS+ pin and BUS– pin) is 20 mV or lower (low level). Logic “0”: Potential difference between bus lines (BUS+ pin and BUS– pin) is 120 mV or higher (high level). Preparation period: The first or subsequent low-level (logic “1”) period Synchronous period: The next high-level (logic “0”) period Data period: The period that expresses the bit value (logic “1”: low level; logic “0”: high level) The synchronous period and data period have approximately the same length. The IEBus uses bit-by-bit synchronization. The specifications for the total bit time and the periods allocated to the bits depend on the type of transfer bit, and on whether the unit is the master unit or the slave unit. 5 Preparation Period Synchronous Period Data Period Logic "1" Logic "0" Preparation Period Synchronous Period Data Period |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
